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PIC16F716 Data Sheet
8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM
(c) 2007 Microchip Technology Inc.
DS41206B
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41206B-page ii
(c) 2007 Microchip Technology Inc.
PIC16F716
8-bit Flash-based Microcontroller with A/D Controller and Enhanced Capture/Compare PWM
Microcontroller Core Features:
* High-performance RISC CPU * Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Interrupt capability (up to 7 internal/external interrupt sources) * 8-level deep hardware stack * Direct, Indirect and Relative Addressing modes
Low-Power Features:
* Standby Current: - 100 nA @ 2.0V, typical * Operating Current: - 14 A @ 32 kHz, 2.0V, typical - 120 A @ 1 MHz, 2.0V, typical * Watchdog Timer Circuit: - 1 A @ 2.0V, typical * Timer1 Oscillator Current: - 3.0 A @ 32 kHz, 2.0V, typical
Special Microcontroller Features:
* Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Dual level Brown-out Reset circuitry - 2.5 VBOR (Typical) - 4.0 VBOR (Typical) * Programmable code protection * Power-Saving Sleep mode * Selectable oscillator options * Fully static design * In-Circuit Serial ProgrammingTM (ICSPTM)
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler can be incremented during Sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Enhanced Capture, Compare, PWM module: - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM maximum resolution is 10-bit - Enhanced PWM: - Single, Half-Bridge and Full-Bridge modes - Digitally programmable dead-band delay - Auto-shutdown/restart * 8-bit multi-channel Analog-to-Digital Converter * 13 I/O pins with individual direction control * Programmable weak pull-ups on PORTB
CMOS Technology:
* Wide operating voltage range: - Industrial: 2.0V to 5.5V - Extended: 3.0V to 5.5V * High Sink/Source Current 25/25 mA * Wide temperature range: - Industrial: -40C to 85C - Extended: -40C to 125C
Device PIC16F716
Memory Flash 2048 x 14 Data 128 x 8
I/O 13
8-bit A/D (ch) 4
Timers 8/16 2/1
PWM (outputs) 1/2/4
VDD Range 2.0V-5.5V
(c) 2007 Microchip Technology Inc.
DS41206B-page 1
PIC16F716
18-Pin Diagram
18-pin PDIP, SOIC RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD RB7/P1D RB6/P1C RB5/P1B RB4/ECCPAS0
RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS RB0/INT/ECCPAS2 RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1/P1A
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
TABLE 1:
I/O RA0 RA1 RA2 RA3 RA4 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 -- -- -- -- -- Pin 17 18 1 2 3 6 7 8 9 10 11 12 13 14 5 4 16 15
18-PIN PDIP, SOIC SUMMARY
Analog AN0 AN1 AN2 AN3/VREF -- -- -- -- -- -- -- -- -- -- -- -- -- -- ECCP -- -- -- -- -- ECCPAS2 -- -- CCP1/P1A ECCPAS0 P1B P1C P1D -- -- -- -- -- Timer -- -- -- -- T0CKI -- T1CKI T1OSI -- -- -- -- -- -- -- -- -- -- Interrupts -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- Pull-ups -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- Basic -- -- -- -- -- -- -- -- -- -- -- ICSPCLK ICSPDAT VDD VSS MCLR/VPP OSC1/CLKIN OSC2/CLKOUT
PIC16F716
DS41206B-page 2
(c) 2007 Microchip Technology Inc.
PIC16F716
20-Pin Diagram
20-pin SSOP RA2/AN2 RA3/AN3/VREF RA4/T0CKI MCLR/VPP VSS VSS RB0/INT/ECCPAS2 RB1/T1OSO/T1CKI RB2/T1OSI RB3/CCP1/P1A 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT VDD VDD RB7/P1D RB6/P1C RB5/P1B RB4/ECCPAS0
TABLE 2:
I/O RA0 RA1 RA2 RA3 RA4 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 -- -- -- -- -- -- -- Pin 19 20 1 2 3 7 8 9 10 11 12 13 14 15 16 5 6 4 18 17
20-PIN SSOP SUMMARY
Analog AN0 AN1 AN2 AN3/VREF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ECCP -- -- -- -- -- ECCPAS2 -- -- CCP1/P1A ECCPAS0 P1B P1C P1D -- -- -- -- -- -- -- Timer -- -- -- -- T0CKI -- T1CKI T1OSI -- -- -- -- -- -- -- -- -- -- -- -- Interrupts -- -- -- -- -- INT -- -- -- IOC IOC IOC IOC -- -- -- -- -- -- -- Pull-ups -- -- -- -- -- Y Y Y Y Y Y Y Y -- -- -- -- -- -- -- Basic -- -- -- -- -- -- -- -- -- -- -- ICSPCLK ICSPDAT VDD VDD VSS VSS MCLR/VPP OSC1/CLKIN OSC2/CLKOUT
(c) 2007 Microchip Technology Inc.
PIC16F716
DS41206B-page 3
PIC16F716
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 7 3.0 I/O Ports ..................................................................................................................................................................................... 19 4.0 Timer0 Module ........................................................................................................................................................................... 27 5.0 Timer1 Module with Gate Control............................................................................................................................................... 29 6.0 Timer2 Module ........................................................................................................................................................................... 35 7.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 37 8.0 Enhanced Capture/Compare/PWM Module ............................................................................................................................... 47 9.0 Special Features of the CPU ...................................................................................................................................................... 61 10.0 Instruction Set Summary ............................................................................................................................................................ 77 11.0 Development Support................................................................................................................................................................. 87 12.0 Electrical Characteristics ............................................................................................................................................................ 91 13.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 107 14.0 Packaging Information.............................................................................................................................................................. 121 Appendix A: Revision History............................................................................................................................................................. 125 Appendix B: Conversion Considerations............................................................................................................................................ 125 Appendix C: Migration from Base-line to Mid-Range Devices ........................................................................................................... 126 The Microchip Web Site ..................................................................................................................................................................... 127 Customer Change Notification Service .............................................................................................................................................. 127 Customer Support .............................................................................................................................................................................. 127 Reader Response .............................................................................................................................................................................. 128 Index .................................................................................................................................................................................................. 129 Product Identification System............................................................................................................................................................. 133
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DS41206B-page 4
(c) 2007 Microchip Technology Inc.
PIC16F716
1.0 DEVICE OVERVIEW
This document contains device specific information for the PIC16F716. Figure 1-1 is the block diagram for the PIC16F716 device. The pinouts are listed in Table 1-1.
FIGURE 1-1:
PIC16F716 BLOCK DIAGRAM
13 Flash 2K x 14 Program Memory Program Counter Data Bus 8 PORTA RA0 RA11 RA2 RA3 RA4 PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7
8 Level Stack (13-bit)
Program Bus
RAM 128 x 8 File Registers RAM Addr(1) 9
14 Instruction Reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR Reg 8 3 STATUS Reg
Power-up Timer Instruction Decode and Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
MUX
ALU 8 W Reg
MCLR Timer1
VDD, VSS Timer2
Timer0
Enhanced CCP (ECCP) Note 1: Higher order bits are from the STATUS register.
A/D
(c) 2007 Microchip Technology Inc.
DS41206B-page 5
PIC16F716
TABLE 1-1:
Name MCLR/VPP
PIC16F716 PINOUT DESCRIPTION
Function MCLR VPP Input Type Output Type ST P XTAL CMOS ST XTAL -- TTL AN TTL AN TTL AN TTL AN AN ST ST TTL ST ST TTL -- ST TTL XTAL TTL ST -- TTL ST TTL -- TTL -- TTL -- P P -- -- -- -- -- -- CMOS CMOS -- CMOS -- CMOS -- CMOS -- -- OD -- CMOS -- -- CMOS XTAL -- CMOS -- CMOS CMOS CMOS CMOS -- CMOS CMOS CMOS CMOS CMOS CMOS -- -- Description Master clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input Oscillator crystal input External clock source input RC Oscillator mode Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. Bidirectional I/O Analog Channel 0 input Bidirectional I/O Analog Channel 1 input Bidirectional I/O Analog Channel 2 input Bidirectional I/O Analog Channel 3 input A/D reference voltage input Bidirectional I/O. Open drain when configured as output. Timer0 external clock input Bidirectional I/O. Programmable weak pull-up. External Interrupt ECCP Auto-Shutdown pin Bidirectional I/O. Programmable weak pull-up. Timer1 oscillator output. Connects to crystal in Oscillator mode. Timer1 external clock input Bidirectional I/O. Programmable weak pull-up. Timer1 oscillator input. Connects to crystal in Oscillator mode. Bidirectional I/O. Programmable weak pull-up. Capture1 input, Compare1 output, PWM1 output. PWM P1A output Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange. ECCP Auto-Shutdown pin Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange. PWM P1B output Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange. ST input when used as ICSP programming clock. PWM P1C output Bidirectional I/O. Programmable weak pull-up. Interrupt-onchange. ST input when used as ICSP programming data. PWM P1D output Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. OD = Open drain ST = Schmitt Trigger input with CMOS levels CMOS = CMOS compatible input or output
OSC1/CLKIN
OSC1 CLKIN CLKIN
OSC2/CLKOUT
OSC2 CLKOUT
RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
RA0 AN0 RA1 AN1 RA2 AN2 RA3 AN3 VREF
RA4/T0CKI RB0/INT/ECCPAS2
RA4 T0CKI RB0 INT ECCPAS2
RB1/T1OSO/T1CKI
RB1 T1OSO T1CKI
RB2/T1OSI RB3/CCP1/P1A
RB2 T1OSI RB3 CCP1 P1A
RB4/ECCPAS0
RB4 ECCPAS0
RB5/P1B
RB5 P1B
RB6/P1C
RB6 P1C
RB7/P1D
RB7 P1D
VSS VDD Legend: I = Input O = Output P = Power
VSS VDD
AN = Analog input or output TTL = TTL compatible input XTAL = Crystal
DS41206B-page 6
(c) 2007 Microchip Technology Inc.
PIC16F716
2.0 MEMORY ORGANIZATION
2.2 Data Memory Organization
There are two memory blocks in the PIC16F716 device. Each block (program memory and data memory) has its own bus so that concurrent access can occur. The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 and RP0 of the STATUS register are the bank select bits. RP<1:0>(1) (Status<6:5>) 00 01 10 11 Note 1: 2: Bank 0 1 2(2) 3(2)
2.1
Program Memory Organization
The PIC16F716 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16F716 has 2K x 14 words of program memory. Accessing a location above the physically implemented address will cause a wrap-around. The Reset vector is at 0000h and the interrupt vector is at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP AND STACK OF PIC16F716
PC<12:0>
Maintain Status bit 6 clear to ensure upward compatibility with future products. Not implemented
CALL, RETURN RETFIE, RETLW
13
Stack Level 1
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. The upper 16 bytes of GPR space and some "high use" Special Function Registers in Bank 0 are mirrored in Bank 1 for code reduction and quicker access.
Stack Level 8 Reset Vector 0000h
User Memory Space
Interrupt Vector
0004h 0005h
On-chip Program Memory 07FFh 0800h 1FFFh
(c) 2007 Microchip Technology Inc.
DS41206B-page 7
PIC16F716
2.2.1 GENERAL PURPOSE REGISTER FILE FIGURE 2-2:
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h ADRES ADCON0 General Purpose Registers 80 Bytes 6Fh 70h 7Fh 16 Bytes Bank 0 Accesses 70-7Fh Bank 1 ADCON1 General Purpose Registers 32 Bytes CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS TMR1L TMR1H T1CON TMR2 T2CON PR2 PCON PCLATH INTCON PIR1 PCLATH INTCON PIE1 INDF(1) TMR0 PCL STATUS FSR PORTA PORTB INDF(1) PCL STATUS FSR TRISA TRISB
REGISTER FILE MAP
File Address 80h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h BFh C0h EFh F0h FFh OPTION_REG 81h
The register file can be accessed either directly or indirectly through the File Select Register FSR (Section 2.5 "Indirect Addressing, INDF and FSR Registers").
Unimplemented data memory locations, read as `0'. Note 1: Not a physical register.
DS41206B-page 8
(c) 2007 Microchip Technology Inc.
PIC16F716
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1. The Special Function Registers can be classified into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.
TABLE 2-1:
Address 00h 01h 02h 03h 04h 05h 06h 07h-09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h-14h 15h 16h 17h 18h 19h 1Ah-1Dh 1Eh 1Fh Legend: Note 1: 2: 3: 4: 5: 6: 7: 8: Name INDF(1) TMR0 PCL(1)
SPECIAL FUNCTION REGISTER SUMMARY BANK 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 xxxx xxxx 0000 0000 PD RA3 RB3 Z RA2 RB2 DC RA1 RB1 C RA0 RB0 0001 1xxx xxxx xxxx RA4 RB4 ---x 0000 xxxx xxxx -- -- PEIE ADIF -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF CCP1IF INTF TMR2IF RBIF TMR1IF ---0 0000 0000 000x -0-- -000 -- xxxx xxxx xxxx xxxx TMR1CS T2CKPS1 TMR1ON T2CKPS0 --00 0000 0000 0000 TMR2ON -000 0000 -- xxxx xxxx xxxx xxxx CCP1M3 PDC3 PSSAC1 CCP1M2 PDC2 PSSAC0 CCP1M1 PDC1 PSSBD1 CCP1M0 PDC0 PSSBD0 0000 0000 0000 0000 00-0 0000 -- xxxx xxxx CHS2 CHS1 CHS0 GO/DONE --(7) ADON 0000 0000 37 41 48 48 48 60 57 29 29 32 35 36 17 13 15 Page 18 27 17 11 18 19 21
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 module's register Program Counter's (PC) Least Significant Byte IRP(4) -- RB7 Unimplemented -- GIE -- RP1(4) -- RB6 RP0 --(7) RB5 TO
STATUS(1) FSR(1) PORTA(5,6) PORTB -- PCLATH(1,2) INTCON(1) PIR1 -- TMR1L TMR1H T1CON TMR2 T2CON -- CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS -- ADRES ADCON0
(5,6)
Indirect Data Memory Address Pointer
Unimplemented Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- -- TOUTPS3 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Timer2 Module's Register TOUTPS2 TOUTPS1 TOUTPS0 Unimplemented Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 PRSEN P1M0 PDC6 DC1B1 PDC5 --(8) DC1B0 PDC4 ECCPAS0
ECCPASE ECCPAS2 Unimplemented A/D Result Register ADCS1 ADCS0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', Shaded locations are unimplemented, read as `0'. These registers can be addressed from either bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset. The IRP and RP1 bits are reserved. Always maintain these bits clear. On any device Reset, these pins are configured as inputs. This is the value that will be in the PORT output latch. Reserved bits, do not use. ECCPAS1 bit is not used on PIC16F716.
(c) 2007 Microchip Technology Inc.
DS41206B-page 9
PIC16F716
TABLE 2-2:
Address 80h 81h 82h 83h 84h 85h 86h 87h-89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh-91h 92h 93h-9Eh 9Fh Legend: Note 1: 2: 3: 4: 5: 6: 7: PR2 -- ADCON1
SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 1111 1111 0000 0000 PD TRISA3 TRISB3 Z TRISA2 TRISB2 DC TRISA1 TRISB1 C TRISA0 TRISB0 0001 1xxx xxxx xxxx ---1 1111 1111 1111 -- -- T0IE -- Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- T0IF CCP1IE INTF TMR2IE RBIF TMR1IE ---0 0000 0000 000x -0-- -000 -- -- -- -- -- POR BOR ---- --qq -- 1111 1111 -- -- -- -- PCFG2 PCFG1 PCFG0 ---- -000 42 35, 52 16 17 13 14 Page 18 12 17 11 18 19 21
INDF(1) OPTION_REG PCL(1) STATUS(1) FSR(1) TRISA TRISB -- PCLATH(1,2) INTCON(1) PIE1 -- PCON --
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU IRP(4) -- TRISB7 -- GIE -- INTEDG RP1(4) -- TRISB6 -- PEIE ADIE T0CS T0SE PSA PS2 PS1 PS0
Program Counter's (PC) Least Significant Byte RP0 --(7) TRISB5 TO TRISA4 TRISB4
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented -- --
Unimplemented Timer2 Period Register Unimplemented -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', Shaded locations are unimplemented, read as `0'. These registers can be addressed from either bank. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset. The IRP and RP1 bits are reserved. Always maintain these bits clear. On any device Reset, these pins are configured as inputs. This is the value that will be in the PORT output latch. Reserved bits, do not use.
DS41206B-page 10
(c) 2007 Microchip Technology Inc.
PIC16F716
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any Status bits, see the "Instruction Set Summary." Note 1: The PIC16F716 does not use bits IRP and RP1 of the STATUS register. Maintain these bits clear to ensure upward compatibility with future products. 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction.
REGISTER 2-1:
Reserved IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5
STATUS: STATUS REGISTER
Reserved RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: This bit is reserved and should be maintained as `0' RP1: This bit is reserved and should be maintained as `0' RP0: Register Bank Select bit (used for direct addressing) 1 = Bank 1 (80h-FFh) 0 = Bank 0 (00h-7Fh) TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions), For Borrow, the polarity is reversed. 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
(c) 2007 Microchip Technology Inc.
DS41206B-page 11
PIC16F716
2.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for the Timer0 register, assign the prescaler to the Watchdog Timer. The OPTION register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: Timer0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
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2.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON Register is a readable and writable register which contains various enable and flag bits for the TMR0 register overflow, RB Port change and external RB0/INT pin interrupts.
REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE(1) R/W-0 T0IF
(2)
R/W-0 INTF
R/W-x RBIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: PORTB Change Interrupt Enable bit(1) 1 = Enables the PORTB change interrupt 0 = Disables the PORTB change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: PORTB Change Interrupt Flag bit 1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in software) 0 = None of the PORTB general purpose I/O pins have changed state IOCB register must also be enabled. T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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2.2.2.4 PIE1 Register
Note: This register contains the individual enable bits for the peripheral interrupts. Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
REGISTER 2-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE U-0 -- U-0 -- U-0 -- R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt Unimplemented: Read as `0' CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: Timer2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 5-3 bit 2
bit 1
bit 0
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2.2.2.5 PIR1 Register
This register contains the individual flag bits for the peripheral interrupts. Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-5:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0 ADIF R/W-0 -- R/W-0 -- R/W-0 -- U-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIF: A/D Interrupt Flag bit 1 = A/D conversion complete 0 = A/D conversion has not completed or has not been started Unimplemented: Read as `0' CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: Timer2 to PR2 Match Interrupt Flag bit 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match has not occurred TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software) 0 = Timer1 has not overflowed
bit 5-3 bit 2
bit 1
bit 0
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2.2.2.6 PCON Register
Note: The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. These devices contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition. If the BOREN Configuration bit is set, BOR is `1' on Power-on Reset and reset to `0' when a Brown-out condition occurs. BOR must then be set by the user and checked on subsequent Resets to see if it is clear, indicating that another Brown-out has occurred. If the BOREN Configuration bit is clear, BOR is unknown on Power-on Reset.
REGISTER 2-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
PCON: POWER CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0
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2.3 PCL and PCLATH
FIGURE 2-3:
PCH 12 87 PCLATH<4:0> 5 PCLATH 12 PCH 1110 PCL 87 11 0 GOTO, CALL PCLATH<4:3> 2 PCLATH Opcode <10:0>
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in Figure 2-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH).
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0 Instruction with PCL as Destination ALU
8
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xFF to 0x00 in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, "Implementing a Table Read" (DS00556).
2.4
Stack
The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Mid-range devices have an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space, and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed 8 times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
2.3.2
PROGRAM MEMORY PAGING
The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper bit of the address is provided by PCLATH<3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bit is programmed so that the desired program memory page is addressed. If a RETURN from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the RETURN instructions (which POPs the address from the stack).
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2.5 Indirect Addressing, INDF and FSR Registers
EXAMPLE 2-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x20 FSR INDF FSR FSR,4 NEXT ;initialize pointer ;to RAM ;clear RAM & FSR ;inc pointer ;all done? ;no, clear next ;yes, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
NEXT
EXAMPLE 2-1:
* * * *
INDIRECT ADDRESSING
CONTINUE
MOVLW MOVWF CLRF INCF BTFSS GOTO :
Register file 05 contains the value 10h Register file 06 contains the value 0Ah Load the value 05 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 06) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although Status bits may be affected). A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit of the STATUS register, as shown in Figure 2-4. However, IRP is not used in the PIC16F716.
FIGURE 2-4:
RP1: RP0 (2) bank select 6
DIRECT/INDIRECT ADDRESSING
Direct Addressing from opcode 0 IRP (2) location select 00 00h 01 80h 10 100h 11 180h bank select location select Indirect Addressing 7 FSR register 0
Data Memory(1)
(3)
(3)
7Fh Bank 0 Note 1: 2: 3:
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
For register file map detail see Figure 2-2. Maintain clear for upward compatibility with future products. Not implemented.
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3.0 I/O PORTS
EXAMPLE 3-1:
BCF CLRF STATUS, RP0 PORTA
INITIALIZING PORTA
; ;Initialize PORTA by ;clearing output ;data latches ;Select Bank 1 ;Value used to ;initialize data ;direction ;Set RA<3:0> as inputs ;RA<4> as outputs ;Return to Bank 0
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
3.1
PORTA and the TRISA Register
BSF MOVLW
STATUS, RP0 0xEF
PORTA is a 5-bit wide bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the PORT data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. PORTA pins, RA<3:0>, are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as `0'.
MOVWF BCF
TRISA STATUS, RP0
FIGURE 3-1:
DATA BUS
BLOCK DIAGRAM OF RA<3:0>
Q VDD VDD
D
WR PORT
CK
Q
Data Latch D WR TRIS
P
Q
N
I/O pin
CK
Q
VSS
VSS
TRIS Latch
Analog Input mode
RD TRIS Q D
TTL Input Buffer
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
RD PORT
EN
Note:
Setting RA3:0 to output while in Analog mode will force pins to output contents of data latch.
To A/D Converter
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FIGURE 3-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
DATA BUS WR PORT
Data Latch D CK Q RA4/T0CKI
Q
N VSS
TRIS Latch D WR TRIS CK Q VSS
Q
Schmitt Trigger Input Buffer
RD TRIS Q D EN EN RD PORT
Timer0 Clock Input
TABLE 3-1:
Name PORTA TRISA ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 RA4 -- Bit 3 RA3 -- Bit 2 RA2 PCFG2 Bit 1 RA1 PCFG1 Bit 0 RA0 Value on POR, BOR Value on all other Resets
---x 0000 ---u uuuu
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
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3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTB pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (such as BSF, BCF, XORWF) with TRISB as the destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Four of PORTB's pins, RB<7:4>, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB<7:4> pin configured as an output is excluded from the interrupton-change comparison). The input pins, RB<7:4>, are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB<7:4> are OR'ed together to generate the RB Port Change Interrupt with flag bit RBIF of the INTCON register. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: 1. 2. Perform a read of PORTB to end the mismatch condition. Clear flag bit RBIF.
EXAMPLE 3-2:
BCF CLRF
INITIALIZING PORTB
;select Bank 0 ;Initialize PORTB by ;clearing output ;data latches ;Select Bank 1 ;Value used to ;initialize data ;direction ;Set RB<3:0> as inputs ;RB<5:4> as outputs ;RB<7:6> as inputs
STATUS, RP0 PORTB
BSF MOVLW
STATUS, RP0 0xCF
MOVWF
TRISB
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU of the OPTION register. The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.
FIGURE 3-3:
BLOCK DIAGRAM OF RB0/INT/ECCPAS2 PIN
VDD VDD weak P pull-up
RBPU(1) DATA BUS WR PORT Data Latch D Q CK TRIS Latch D Q WR TRIS CK
RB0/ INT/ ECCPAS2 VSS
TTL Input Buffer RD TRIS Q RD PORT D EN Schmitt Trigger Buffer RD PORT ECCPAS2: ECCP Auto-shutdown input Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
RB0/INT
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FIGURE 3-4: BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
VDD T1OSCEN RBPU(1) weak P pull-up VDD DATA BUS WR PORTB Data Latch D CK Q Q RB1/T1OSO/T1CKI
TRIS Latch D WR TRISB CK Q Q VSS
RD TRISB T1OSCEN TTL Buffer Q D EN RD PORTB T1OSI (From RB2) TMR1 oscillator To Timer1 clock input ST Buffer Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
FIGURE 3-5:
BLOCK DIAGRAM OF RB2/T1OSI PIN
RBPU(1) VDD weak P pull-up VDD
T1OSCEN Data Latch DATA BUS WR PORTB D CK Q Q
RB2/T1OSI
TRIS Latch D WR TRISB CK Q Q VSS
RD TRIS T1OSCEN TTL Buffer Q D EN RD PORTB T1OSO (To RB1) Note 1: TMR1 Oscillator
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
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FIGURE 3-6: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN
VDD [PWMA(P1A) / CCP1 Compare] Output Enable [PWMA(P1A) / CCP1 Compare] Output RBPU(1) weak P pull-up VDD
1 RB3/CCP1/P1A 0
PWMA(P1A) Auto-shutdown tri-state DATA BUS WR PORTB Data Latch D CK Q Q VSS
TRIS Latch D WR TRISB CK Q Q
RD TRIS TTL Buffer Q D EN RD PORTB Schmitt Trigger Buffer CCP - Capture input
Note
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
FIGURE 3-7:
BLOCK DIAGRAM OF RB4/ECCPAS0 PIN
VDD RBPU(1) DATA BUS WR PORTB Data Latch D Q CK TRIS Latch D Q WR TRISB CK TTL Buffer weak P pull-up VDD
RB4/ECCPAS0
VSS
ST Buffer
RD TRIS Q RD PORT Set RBIF
Latch D EN Q1
From other RB<7:4> pins
Q
D RD PORT EN Q3
Note
1:
ECCPAS0: ECCP Auto-Shutdown input
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit of the OPTION register.
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FIGURE 3-8: BLOCK DIAGRAM OF RB5/P1B PIN
VDD PWMB(P1B) Enable PWMB(P1B) Data out PWMB(P1B) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB CK TRIS Latch D Q WR TRISB CK Q VSS TTL Buffer RBPU(1) weak P pull-up VDD RB5/P1B
1 0
RD TRISB Q RD PORTB Set RBIF
Latch D EN Q1
From other RB<7:4> pins
Q
D EN RD PORTB Q3
Note
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
FIGURE 3-9:
BLOCK DIAGRAM OF RB6/P1C PIN
VDD PWMC(P1C) Enable PWMC(P1C) Data out PWMC(P1C) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB CK TRIS Latch D Q WR TRISB CK Q ST Buffer VSS TTL Buffer RBPU(1) weak P pull-up VDD RB6/P1C
1 0
RD TRISB Q RD PORTB Set RBIF
Latch D EN Q1
From other RB<7:4> pins
Q
D EN RD PORTB Q3
ICSPC - In-Circuit Serial ProgrammingTM Clock Input
Note
1:
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION register).
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FIGURE 3-10: BLOCK DIAGRAM OF RB7/P1D PIN
VDD PWMD(P1D) Enable PWMD(P1D) Data out PWMD(P1D) Auto-shutdown tri-state Data Latch DATA BUS D Q WR PORTB CK TRIS Latch D Q WR TRISB CK Q ST Buffer VSS TTL Buffer RBPU(1) weak P pull-up VDD RB7/P1D
1 0
RD TRISB Q RD PORTB Set RBIF
Latch D EN Q1
From other RB<7:4> pins
Q
D EN RD PORTB Q3
Note
1:
ICSPD - In-Circuit Serial ProgrammingTM Data Input
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit of the OPTION register.
TABLE 3-2:
Name PORTB TRISB OPTION_REG Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 TRISB7 RBPU Bit 6 RB6 TRISB6 INTEDG Bit 5 RB5 TRISB5 T0CS Bit 4 RB4 TRISB4 T0SE Bit 3 RB3 TRISB3 PSA Bit 2 RB2 TRISB2 PS2 Bit 1 RB1 TRISB1 PS1 Bit 0 RB0 TRISB0 PS0 Value on POR, BOR xxxx xxxx 1111 1111 1111 1111 Value on all other Resets uuuu uuuu 1111 1111 1111 1111
x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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NOTES:
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4.0 TIMER0 MODULE
4.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
4.1.1
8-BIT TIMER MODE
When used as a timer, the Timer0 module will increment every instruction cycle (without prescaler). Timer mode is selected by clearing the T0CS bit of the OPTION register to `0'. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
Figure 4-1 is a block diagram of the Timer0 module.
4.1.2
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to `1'.
FIGURE 4-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus 0 1 1 T0CKI pin T0SE T0CS 0 0 8-bit Prescaler 1 8 PSA Set Flag bit T0IF on Overflow Sync 2 TCY TMR0 8
PSA WDTE
PS<2:0>
1 WDT Time-out 0
31 kHz INTOSC
Watchdog Timer
PSA
Note
1: 2:
T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. WDTE bit is in the Configuration Word register.
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4.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a `0'. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be assigned to the WDT module. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. When the prescaler is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (see Example 4-2).
EXAMPLE 4-2:
CLRWDT
CHANGING PRESCALER (WDT TIMER0)
;Clear WDT and ;prescaler BANKSEL OPTION_REG ; MOVLW b'11110000' ;Mask TMR0 select and ANDWF OPTION_REG,W ;prescaler bits IORLW b'00000011' ;Set prescale to 1:16 MOVWF OPTION_REG ;
4.1.4
TIMER0 INTERRUPT
4.1.3.1
Switching Prescaler Between Timer0 and WDT Modules
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit must be cleared in software. The Timer0 interrupt enable is the T0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.
As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device Reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 4-1, must be executed.
4.1.5
USING TIMER0 WITH AN EXTERNAL CLOCK
EXAMPLE 4-1:
BANKSEL CLRWDT CLRF BANKSEL BSF CLRWDT MOVLW ANDWF IORLW MOVWF TMR0 TMR0
CHANGING PRESCALER (TIMER0 WDT)
; ;Clear WDT ;Clear TMR0 and ;prescaler ; ;Select WDT ; ; ;Mask prescaler ;bits ;Set WDT prescaler ;to 1:32
When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 12.0 "Electrical Characteristics".
OPTION_REG OPTION_REG,PSA
b'11111000' OPTION_REG,W b'00000101' OPTION_REG
TABLE 4-1:
Name TMR0 INTCON OPTION_REG TRISA Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE TRISA4 RBIE PSA TRISA3 T0IF PS2 TRISA2 INTF PS1 TRISA1 RBIF PS0 TRISA0 0000 000x 1111 1111 ---1 1111 Value on all other Resets uuuu uuuu 0000 000u 1111 1111 ---1 1111
Timer0 Module Register GIE RBPU -- PEIE INTEDG -- T0IE T0CS --
- = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
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5.0 TIMER1 MODULE WITH GATE CONTROL
5.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer. When used with an external clock source, the module can be used as either a timer or counter.
The Timer1 module is a 16-bit timer/counter with the following features: 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 3-bit prescaler Optional LP oscillator Synchronous or asynchronous operation Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with ECCP) Figure 5-1 is a block diagram of the Timer1 module. * * * * * * *
5.2
Clock Source Selection
The TMR1CS bit of the T1CON register is used to select the clock source. When TMR1CS = 0, the clock source is FOSC/4. When TMR1CS = 1, the clock source is supplied externally.
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
Set flag bit TMR1IF on Overflow TMR1H
TMR1(2) TMR1L
0 1
Synchronized clock input
T1OSC RB1/T1OSO/T1CKI
TMR1ON on/off 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock
T1SYNC Prescaler 1, 2, 4, 8 Synchronize det Sleep input
(3)
RB2/T1OSI
0 2 T1CKPS<1:0>
Note 1: 2: 3:
ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI. Timer1 register increments on rising edge. Synchronize does not operate while in Sleep.
5.2.1
INTERNAL CLOCK SOURCE
5.2.2
EXTERNAL CLOCK SOURCE
When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler.
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after one or more of the following conditions: * Timer1 is enabled after POR or BOR Reset * A write to TMR1H or TMR1L * T1CKI is high when Timer1 is disabled and when Timer1 is reenabled T1CKI is low. See Figure 5-2.
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5.3 Timer1 Prescaler
5.5.1
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L.
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
5.4
Timer1 Oscillator
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.
A low-power 32.768 kHz crystal oscillator is built-in between pins T1OSI (input) and T1OSO (output). The oscillator is enabled by setting the T1OSCEN control bit of the T1CON register. The oscillator will continue to run during Sleep. The Timer1 oscillator is shared with the system LP oscillator. Thus, Timer1 can use this mode only when the primary system clock is derived from the internal oscillator or when in LP oscillator mode. The user must provide a software time delay to ensure proper oscillator start-up. TRISB1 and TRISB2 bits are set when the Timer1 oscillator is enabled. RB1 and RB2 bits read as `0' and TRISB1 and TRISB2 bits read as `1'. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
5.6
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * Timer1 interrupt enable bit of the PIE1 register * PEIE bit of the INTCON register * GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
5.5
Timer1 Operation in Asynchronous Counter Mode 5.7
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 5.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note 1: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 2: In Asynchronous Counter mode, Timer1 can not be used as a time base for the Capture or Compare modes of the ECCP module.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * TMR1ON bit of the T1CON register must be set * TMR1IE bit of the PIE1 register must be set * PEIE bit of the INTCON register must be set The device will wake-up on an overflow and execute the next instruction. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine (0004h).
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5.8 ECCP Capture/Compare Time Base 5.9 ECCP Special Event Trigger
If a ECCP is configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The ECCP module may still be configured to generate a ECCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1. Timer1 should be synchronized to the FOSC to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the ECCP, the write will take precedence. For more information, see Section 8.0 "Enhanced Capture/Compare/PWM Module".
The ECCP module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see Section 8.0 "Enhanced Capture/Compare/PWM Module".
FIGURE 5-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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5.10 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 5-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 5-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
T1CON: TIMER 1 CONTROL REGISTER
U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale Value 10 = 1:4 Prescale Value 01 = 1:2 Prescale Value 00 = 1:1 Prescale Value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is disabled T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1CKI pin (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 3
bit 2
bit 1
bit 0
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TABLE 5-1:
Name INTCON PIE1 PIR1 TMR1H TMR1L T1CON Legend: Bit 7 GIE -- --
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 6 PEIE ADIE ADIF Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE -- -- Bit 2 T0IF CCP1IE CCP1IF Bit 1 INTF TMR2IE TMR2IF Bit 0 RBIF TMR1IE TMR1IF Value on POR, BOR 0000 000x -0-- -000 -0-- -000 xxxx xxxx xxxx xxxx TMR1CS TMR1ON --00 0000 Value on all other Resets 0000 000x -0-- -000 -0-- -000 uuuu uuuu uuuu uuuu --uu uuuu
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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NOTES:
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6.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following features: * * * * * 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a `1'. Timer2 is turned off by clearing the TMR2ON bit to a `0'. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The Timer2 postscaler is controlled by the TOUTPS bits in the T2CON register. The prescaler and postscaler counters are cleared when: * A write to TMR2 occurs. * A write to T2CON occurs. * Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written.
See Figure 6-1 for a block diagram of Timer2.
6.1
Timer2 Operation
The clock input to the Timer2 module is the system instruction clock (FOSC/4). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 will increment from 00h until it matches the value in PR2. When a match occurs, two things happen: * TMR2 is reset to 00h on the next increment cycle * The Timer2 postscaler is incremented The match output of the Timer2/PR2 comparator is then fed into the Timer2 postscaler. The postscaler has postscale options of 1:1 to 1:16 inclusive. The output of the Timer2 postscaler is used to set the TMR2IF interrupt flag bit in the PIR2 register.
FIGURE 6-1:
TIMER2 BLOCK DIAGRAM
TMR2 Output Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16 2 T2CKPS<1:0>
TMR2 Comparator
Reset Postscaler 1:1 to 1:16 4 TOUTPS<3:0>
EQ
PR2
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REGISTER 6-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T2CON: TIMER 2 CONTROL REGISTER
R/W-0 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
TOUTPS3
Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2
bit 1-0
TABLE 6-1:
Name INTCON PIE1 PIR1 PR2 TMR2 T2CON Legend: Bit 7 GIE -- --
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 6 PEIE ADIE ADIF Bit 5 T0IE -- -- Bit 4 INTE -- -- Bit 3 RBIE -- -- Bit 2 T0IF CCP1IE CCP1IF Bit 1 INTF TMR2IE TMR2IF Bit 0 RBIF TMR1IE TMR1IF Value on POR, BOR 0000 000x -0-- -000 -0-- -000 1111 1111 0000 0000 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 TOUTPS1 Value on all other Resets 0000 000x -0-- -000 -0-- -000 1111 1111 0000 0000 -000 0000
Timer2 Module Period Register Holding Register for the 8-bit TMR2 Register -- TOUTPS3 TOUTPS2
x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used for Timer2 module.
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7.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. Figure 7-1 shows the block diagram of the ADC.
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES).
FIGURE 7-1:
ADC BLOCK DIAGRAM
VDD PFCG<2:0> (ADCON1 register)
VREF
RA0/AN0 RA1/AN1 RA2/AN2 RA3/VREF/AN3
000 001 010 011 GO/DONE ADC 8
CHS ADON VSS
ADRES
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7.1 ADC Configuration
7.1.3
ADC VOLTAGE REFERENCE
When configuring and using the ADC the following functions must be considered: * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control
The PCFG bits of the ADCON0 register provide independent control of the positive voltage reference. The positive voltage reference can be either VDD or an external voltage source.
7.1.4
CONVERSION CLOCK
7.1.1
PORT CONFIGURATION
The source of the conversion clock is software selectable via the ADCS bits of the ADCON0 register. There are four possible clock options: * * * * FOSC/2 FOSC/8 FOSC/32 FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ADCON1 bits. See the corresponding Port section for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
The time to complete one bit conversion is defined as TAD. One full 8-bit conversion requires 9.5 TAD periods. For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 12.0 "Electrical Characteristics" for more information. Table 7-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
7.1.2
CHANNEL SELECTION
The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 7.2 "ADC Operation" for more information.
TABLE 7-1:
Operation 2 TOSC 8 TOSC 32 TOSC RC Legend: Note 1: 2: 3: 4:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency 20 MHz 100 ns(2) 400 ns(2) 1.6 s 5 MHz 400 ns(2) 1.6 s 6.4 s 1.25 MHz 1.6 s 6.4 s 25.6 s(3) 333.33 kHz 6 s 24 s(3) 96 s(3) ADCS<1:0> 00 01 10
AD Clock Source (TAD)
11 2-6 s(1), (4) 2-6 s(1), (4) 2-6 s(1), (4) 2-6 s(1) Shaded cells are outside of recommended range. The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for Sleep operation only.
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7.1.5 INTERRUPTS
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.
This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 7.1.5 "Interrupts" for more information.
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7.2
7.2.1
ADC Operation
STARTING A CONVERSION
7.2.5
SPECIAL EVENT TRIGGER
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 7.2.6 "A/D Conversion Procedure".
The ECCP Special Event Trigger allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. See Section 8.0 "Enhanced Capture/Compare/ PWM Module" for more information.
7.2.2
COMPLETION OF A CONVERSION
7.2.6
A/D CONVERSION PROCEDURE
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF flag bit * Update the ADRES register with new conversion result
This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (See TRIS register) * Configure pin as analog Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Select result format * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: See Section 7.3 Requirements". "A/D Acquisition
2.
7.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRES register will not be updated with the partially complete Analog-to-Digital conversion sample. Instead, the ADRES register will retain the value of the previous conversion. Additionally, a 2 TAD delay is required before another acquisition can be initiated. Following this delay, an input acquisition is automatically started on the selected channel. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
3.
4. 5. 6.
7.2.4
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.
7. 8.
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7.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 7-1:
R/W-0 ADCS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
ADCON0: A/D CONTROL REGISTER 0
R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCS<1:0>: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (Clock derived from the internal ADC RC oscillator) CHS<2:0>: Analog Channel Select bits 000 = AN0 001 = AN1 010 = AN2 011 = AN3 100 = Reserved, do not use 101 = Reserved, do not use 110 = Reserved, do not use 111 = Reserved, do not use GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress Unimplemented: Read as `0' ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current
bit 5-3
bit 2
bit 1 bit 0
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REGISTER 7-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: A/D CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
Unimplemented: Read as `0' PCFG<2:0>: A/D Port Configuration Control bits. The following table illustrates the effects of the various configurations:
AN3/ RA3 A VREF A VREF D AN2/ RA2 A A D D D AN2/ RA1 A A A A D AN0/ RA0 A A A A D
PCFG<2:0> 0x0 0x1 100 101 11x Legend:
VREF VDD RA3 VDD RA3 VDD
A = Analog input, D = Digital I/O
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7.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 7-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 7-2. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 7-1 may be used. This equation assumes that 1/2 LSb error is used. The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 7-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + [ ( Temperature - 25C ) ( 0.05s/C ) ] The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - ----------- = VCHOLD 2047
--------- RC VAPPLIED 1 - e = VCHOLD -------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - ----------- 2047 - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
Solving for TC:
TC = - CHOLD ( RIC + RSS + RS ) ln(1/2047) = - 10pF ( 1k + 7k + 10k ) ln(0.0004885) = 1.37 s
Therefore: TACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S/C ) ] = 4.67S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 7-2: ANALOG INPUT MODEL
VDD Rs VA ANx CPIN 5 pF VT = 0.6V RIC 1k ILEAKAGE(1) Sampling Switch SS Rss CHOLD = 10 pF VSS
VT = 0.6V
Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: See Section 12.0 "Electrical Characteristics".
6V 5V VDD 4V 3V 2V
RSS
5 6 7 8 9 10 11 Sampling Switch (k)
FIGURE 7-3:
ADC TRANSFER FUNCTION
Full-Scale Range
FFh FEh FDh ADC Output Code FCh FBh Full-Scale Transition 1 LSB ideal
04h 03h 02h 01h 00h 1 LSB ideal VSS Zero-Scale Transition
Analog Input Voltage
VDD/VREF+
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TABLE 7-2:
Name ADCON0 ADCON1 ADRES INTCON PIE1 PIR1 PORTA TRISA Legend:
SUMMARY OF ASSOCIATED ADC REGISTERS
Bit 7 ADCS1 -- GIE -- -- -- -- Bit 6 ADCS0 -- PEIE ADIE ADIF -- -- Bit 5 CHS2 -- T0IE -- -- -- -- Bit 4 CHS1 -- INTE -- -- RA4 TRISA4 Bit 3 CHS0 -- RBIE -- -- RA3 TRISA3 Bit 2 GO/DONE PCFG2 T0IF CCP1IE CCP1IF RA2 TRISA2 Bit 1 -- PCFG1 INTF TMR2IE TMR2IF RA1 TRISA1 Bit 0 ADON PCFG0 RBIF TMR1IE TMR1IF RA0 TRISA0 Value on POR, BOR 0000 0000 ---- -000 xxxx xxxx 0000 000x -0-- -000 -0-- -000 --xx xxxx --11 1111 Value on all other Resets 0000 0000 ---- -000 uuuu uuuu 0000 000x -0-- -000 -0-- -000 --uu uuuu --11 1111
A/D Result Register
x = unknown, u = unchanged, -- = unimplemented read as `0'. Shaded cells are not used for ADC module.
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NOTES:
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8.0 ENHANCED CAPTURE/ COMPARE/PWM MODULE
Note: CCPR1 and CCP1 throughout this document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively.
The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle. Table 8-1 shows the timer resources required by the ECCP module.
TABLE 8-1:
ECCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
ECCP Mode Capture Compare PWM
REGISTER 8-1:
R/W-0 P1M1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
CCP1CON: ENHANCED CCP1 CONTROL REGISTER
R/W-0 P1M0 R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
P1M<1:0>: PWM Output Configuration bits If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. CCP1M<3:0>: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, Special Event Trigger (CCP1IF bit is set; CCP1 resets TMR1 or TMR2) 1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
bit 5-4
bit 3-0
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8.1 Capture Mode
8.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
8.1.3
SOFTWARE INTERRUPT
When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value (see Figure 8-1).
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in operating mode.
8.1.4
CCP PRESCALER
8.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler (see Example 8-1).
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1 register)
EXAMPLE 8-1:
BANKSEL CCP1CON CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Prescaler / 1, 4, 16 CCP1 pin
CCPR1H and Edge Detect Capture Enable TMR1H
CCPR1L
MOVWF
TMR1L
;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; move value and CCP ON CCP1CON ;Load CCP1CON with this ; value
CCP1CON<3:0> System Clock (FOSC)
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TABLE 8-2:
Name
CCPR1L CCPR1H CCP1CON INTCON PIE1 PIR1 PR2 TMR1L TMR1H TMR2 TRISB
REGISTERS ASSOCIATED WITH CAPTURE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR
xxxx xxxx xxxx xxxx CCP1M3 RBIE -- -- CCP1M2 T0IF CCP1IE CCP1IF CCP1M1 INTF TMR2IE TMR2IF CCP1M0 RBIF TMR1IE TMR1IF 0000 0000 0000 000x -0-- -000 -0-- -000 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 INTE -- -- DC1B0
Value on all other Resets
xxxx xxxx xxxx xxxx 0000 0000 0000 000x -0-- -000 -0-- -000 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 1111 1111
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 GIE -- -- P1M0 PEIE ADIE ADIF DC1B1 T0IE -- --
Timer2 Period Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Timer2 module's register TRISB7 TRISB6
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Capture.
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8.2 Compare Mode
8.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 module may: * * * * * Toggle the CCP1 output. Set the CCP1 output. Clear the CCP1 output. Generate a Special Event Trigger. Generate a Software Interrupt. In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.
8.2.3
SOFTWARE INTERRUPT MODE
The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. All Compare modes can generate an interrupt.
When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register).
8.2.4
SPECIAL EVENT TRIGGER
FIGURE 8-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L Q S R Output Logic Comparator TMR1H TMR1L
When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode (see the CCP1CON register). The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMRxIF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.
CCP1 Pin
Match
TRIS Output Enable Special Event Trigger Special Event Trigger will:
* Clear TMR1H and TMR1L registers. * NOT set interrupt flag bit TMR1IF of the PIR1 register. * Set the GO/DONE bit to start the ADC conversion.
8.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch.
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TABLE 8-3:
Name
CCPR1L CCPR1H CCP1CON INTCON PIE1 PIR1 PR2 TMR1L TMR1H TMR2 TRISB
REGISTERS ASSOCIATED WITH COMPARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR
xxxx xxxx xxxx xxxx CCP1M3 RBIE -- -- CCP1M2 T0IF CCP1IE CCP1IF CCP1M1 INTF TMR2IE TMR2IF CCP1M0 RBIF TMR1IE TMR1IF 0000 0000 0000 000x -0-- -000 -0-- -000 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 INTE -- -- DC1B0
Value on all other Resets
xxxx xxxx xxxx xxxx 0000 0000 0000 000x -0-- -000 -0-- -000 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 1111 1111
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 GIE -- -- P1M0 PEIE ADIE ADIF DC1B1 T0IE -- --
Timer2 Period Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Timer2 module's register TRISB7 TRISB6
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the Compare.
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8.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: * * * * PR2 T2CON CCPR1L CCP1CON The PWM output (Figure 8-4) has a time base (period) and a time that the output stays high (duty cycle).
FIGURE 8-4:
Period Pulse Width
CCP PWM OUTPUT
TMR2 = PR2 TMR2 = CCPR1L:CCP1CON<5:4>
In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin. Since the CCP1 pin is multiplexed with the PORT data latch, the TRIS for that pin must be cleared to enable the CCP1 pin output driver. Note: Clearing the CCP1CON register will relinquish CCP1 control of the CCP1 pin.
TMR2 = 0
Figure 8-3 shows a simplified block diagram of PWM operation. Figure 8-4 shows a typical waveform of the PWM signal. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 8.3.7 "Setup for PWM Operation".
FIGURE 8-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H(2) (Slave) CCP1 Comparator
(1)
R S
Q
TMR2
TRIS Comparator
PR2
Clear Timer2, toggle CCP1 pin and latch duty cycle
Note 1:
2:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register.
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8.3.1 PWM PERIOD 8.3.2 PWM DUTY CYCLE
The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 8-1. The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 8-2 is used to calculate the PWM pulse width. Equation 8-3 is used to calculate the PWM duty cycle ratio.
EQUATION 8-1:
PWM PERIOD
(TMR2 Prescale Value)
PWM Period = [ ( PR2 ) + 1 ] * 4 * TOSC *
When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: The Timer2 postscaler (see Section 6.0 "Timer2 Module") is not used in the determination of the PWM frequency.
EQUATION 8-2:
PULSE WIDTH
Pulse Width = ( CCPR1L:CCP1CON<5:4> ) * TOSC * (TMR2 Prescale Value)
EQUATION 8-3:
DUTY CYCLE RATIO
( CCPR1L:CCP1CON<5:4> ) Duty Cycle Ratio = ---------------------------------------------------------------------4 ( PR2 + 1 ) The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2bit latch, then the CCP1 pin is cleared (see Figure 8-3).
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8.3.3 PWM RESOLUTION EQUATION 8-4: PWM RESOLUTION
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 8-4. Note: log [ 4 ( PR2 + 1 ) ] Resolution = ----------------------------------------- bits log ( 2 )
If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.
TABLE 8-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 8-5:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
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8.3.4 OPERATION IN SLEEP MODE 8.3.7 SETUP FOR PWM OPERATION
In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. Disable the PWM pin (CCP1) output drivers by setting the associated TRIS bit. Set the PWM period by loading the PR2 register. Configure the CCP module for the PWM mode by loading the CCP1CON register with the appropriate values. Set the PWM duty cycle by loading the CCPR1L register and DC1B bits of the CCP1CON register. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR1 register. * Set the Timer2 prescale value by loading the T2CKPS bits of the T2CON register. * Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output after a new PWM cycle has started: * Wait until Timer2 overflows (TMR2IF bit of the PIR1 register is set). * Enable the CCP1 pin output driver by clearing the associated TRIS bit.
8.3.5
CHANGES IN SYSTEM CLOCK FREQUENCY
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency.
4. 5.
8.3.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
6.
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8.3.8 ENHANCED PWM AUTOSHUTDOWN MODE
When a shutdown event occurs, two things happen: The ECCPASE bit is set to `1'. The ECCPASE will remain set until cleared in firmware or an auto-restart occurs (see Section 8.3.9 "Auto-Restart Mode"). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state of each pin pair is determined by the PSSAC and PSSBD bits of the ECCPAS register. Each pin pair may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance) The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPASx bits of the ECCPAS register. A shutdown event may be generated by: * A logic `0' on the INT pin * Setting the ECCPASE bit in firmware A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. Refer to Figure 8-5.
FIGURE 8-5:
AUTO-SHUTDOWN BLOCK DIAGRAM
ECCPAS<2:0> PSSAC<0> P1A_DRV 111 110 101 100 PSSAC<1> TRISx P1A 1 0
INT From Comparator C2 From Comparator C1
011 010 001 000 PRSEN PSSBD<1> R From Data Bus Write to ECCPASE D S Q ECCPASE PSSAC<0> P1C_DRV TRISx P1B PSSBD<0> P1B_DRV 1 0
1 0
PSSAC<1> TRISx P1C
PSSBD<0> P1D_DRV
1 0
PSSBD<1> TRISx P1D
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REGISTER 8-2:
R/W-0 ECCPASE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER
R/W-0 U-0 -- R/W-0 ECCPAS0 R/W-0 PSSAC1 R/W-0 PSSAC0 R/W-0 PSSBD1 R/W-0 PSSBD0 bit 0
ECCPAS2
ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in shutdown state 0 = ECCP outputs are operating ECCPAS2: ECCP Auto-Shutdown bit 2 1 = RB0 (INT) pin low level (`0') causes shutdown 0 = RB0 (INT) pin has no effect on ECCP Unimplemented: Read as `0' ECCPAS0: ECCP Auto-Shutdown bit `0' 1 = RB4 pin low level (`0') causes shutdown 0 = RB4 pin has no effect on ECCP PSSACn: Pins P1A and P1C Shutdown State Control bits 00 = Drive pins P1A and P1C to `0' 01 = Drive pins P1A and P1C to `1' 1x = Pins P1A and P1C tri-state PSSBDn: Pins P1B and P1D Shutdown State Control bits 00 = Drive pins P1B and P1D to `0' 01 = Drive pins P1B and P1D to `1' 1x = Pins P1B and P1D tri-state
bit 6
bit 5 bit 4
bit 3-2
bit 1-0
Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period.
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FIGURE 8-6: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
Shutdown Event ECCPASE bit PWM Activity PWM Period Start of PWM Period ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes
8.3.9
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume.
FIGURE 8-7:
Shutdown Event ECCPASE bit PWM Activity
PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
PWM Period Start of PWM Period Shutdown Shutdown Event Occurs Event Clears PWM Resumes
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8.3.10 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 8-8:
Period Pulse Width P1A(2) td P1B(2)
(1)
EXAMPLE OF HALFBRIDGE PWM OUTPUT
Period
In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 8-8 for illustration. The lower seven bits of the associated PWM1CON register (Register 8-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC).
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high.
FIGURE 8-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A
+ V Load + V -
FET Driver P1B
V-
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REGISTER 8-3:
R/W-0 PRSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0 PDC6 R/W-0 PDC5 R/W-0 PDC4 R/W-0 PDC3 R/W-0 PDC2 R/W-0 PDC1 R/W-0 PDC0 bit 0
PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM PDC<6:0>: PWM Delay Count bits PDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active
bit 6-0
TABLE 8-6:
Name
CCPR1L CCPR1H CCP1CON ECCPAS INTCON PIE1 PIR1 PR2 PWM1CON TMR1L TMR1H TMR2 TRISB
REGISTERS ASSOCIATED WITH PWM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR
xxxx xxxx xxxx xxxx CCP1M3 PSSAC1 RBIE -- -- PDC3 CCP1M2 PSSAC0 T0IF CCP1IE CCP1IF PDC2 CCP1M1 PSSBD1 INTF TMR2IE TMR2IF PDC1 CCP1M0 PSSBD0 RBIF TMR1IE TMR1IF PDC0 0000 0000 00-0 0000 0000 000x -0-- -000 -0-- 0000 1111 1111 PDC5 PDC4 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 DC1B0 ECCPAS0 INTE -- --
Value on all other Resets
xxxx xxxx xxxx xxxx 0000 0000 00-0 0000 0000 000x -0-- -000 -0-- -000 1111 1111 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 1111 1111
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M1 ECCPASE GIE -- -- PRSEN P1M0 ECCPAS2 PEIE ADIE ADIF PDC6 DC1B1 -- T0IE -- --
Timer2 Period Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Timer2 Module's Register TRISB7 TRISB6
Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM.
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PIC16F716
9.0 SPECIAL FEATURES OF THE CPU
9.1 Configuration Bits
The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming.
The PIC16F716 device has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. These are: * OSC Selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Sleep * Code protection * ID locations * In-Circuit Serial ProgrammingTM (ICSPTM) The PIC16F716 device has a Watchdog Timer, which can be shut off only through Configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only and is designed to keep the part in Reset while the power supply stabilizes. With these two timers on-chip, most applications need no external Reset circuitry. Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of Configuration bits are used to select various options.
(c) 2007 Microchip Technology Inc.
DS41206B-page 61
PIC16F716
REGISTER 9-1:
-- bit 15
CONFIG: CONFIGURATION WORD REGISTER
-- CP(2) -- -- -- -- -- bit 8
BORV bit 7 Legend: R = Readable bit
BOREN(1)
--
--
PWRTE
WDTE
FOSC1
FOSC0 bit 0
W = Writable bit `1' = Bit is set
P = Programmable' `0' = Bit is cleared
U = Unimplemented bit, read as `0' x = Bit is unknown
-n = Value at POR bit 15-14 bit 13
Unimplemented: Read as `1' CP: Code Protection bit(2) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled Unimplemented: Read as `1' BORV: Brown-out Reset Voltage bit 1 = VBOR set to 4.0V 0 = VBOR set to 2.5V BOREN: Brown-out Reset Selection bits(1) 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `1' PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC<2:0>: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire program memory will be erased when the code protection is turned off.
bit 12-8 bit 7
bit 6
bit 5-4 bit 3
bit 2
bit 1-0
Note 1: 2:
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(c) 2007 Microchip Technology Inc.
PIC16F716
9.2
9.2.1
Oscillator Configurations
OSCILLATOR TYPES
TABLE 9-1:
Mode XT HS
CERAMIC RESONATORS
Ranges Tested: Freq OSC1 (C1) OSC2 (C2)
The PIC16F716 can be operated in four different oscillator modes. The user can program two Configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP - Low-power Crystal XT - Crystal/Resonator HS - High-speed Crystal/Resonator RC - Resistor/Capacitor
Note 1:
455 kHz 68-100 pF 68-100 pF 2.0 MHz 15-68 pF 15-68 pF 4.0 MHz 10-68 pF 10-68 pF 8.0 MHz 15-68 pF 15-68 pF 16.0 MHz 10-22 pF 10-22 pF These values are for design guidance only. See notes at bottom of page.
9.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS
TABLE 9-2:
Osc Type LP XT
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 200 kHz 200 kHz 1 MHz 4 MHz Cap. Range C1 15-33 pF 5-10 pF 47-68 pF 15-33 pF 15-33 pF 15-33 pF 15-33 pF 15-33 pF Cap. Range C2 15-33 pF 5-10 pF 47-68 pF 15-33 pF 15-33 pF 15-33 pF 15-33 pF 15-33 pF
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 9-1). The PIC16F716 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 9-2).
HS
4 MHz 8 MHz 20 MHz
FIGURE 9-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To internal logic
Note 1:
These values are for design guidance only. See notes at bottom of page.
C1(1)
XTAL OSC2 C2(1) Note 1: 2: 3: RS(2)
Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: RS may be required to avoid overdriving crystals with low drive level specification. 4: When using an external clock for the OSC1 input, loading of the OSC2 pin must be kept to a minimum by leaving the OSC2 pin unconnected.
RF(3)
Sleep
PIC16F716
See Table 9-1 and Table 9-2 for recommended values of C1 and C2. A series resistor (RS) may be required. RF varies with the crystal chosen.
FIGURE 9-2:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC16F716 Open OSC2
Clock from ext. system
(c) 2007 Microchip Technology Inc.
DS41206B-page 63
PIC16F716
9.2.3 RC OSCILLATOR
For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-3 shows how the R/C combination is connected to the PIC16F716. A simplified block diagram of the On-chip Reset circuit is shown in Figure 9-5. The PIC(R) microcontrollers have an MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive the MCLR pin low.
9.4
Power-On Reset (POR)
FIGURE 9-3:
VDD REXT
RC OSCILLATOR MODE
A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified (parameter D004). For a slow rise time, see Figure 9-4. When the device starts normal operation (exits the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions.
OSC1 CEXT VSS FOSC/4 Recommended values: 3 k REXT 100 k (VDD 3.0V) 10 k REXT 100 k (VDD 3.0V) CEXT > 20 pF OSC2/CLKOUT
Internal clock PIC16F716
FIGURE 9-4:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD VDD R R1 C MCLR PIC16F716
9.3
Reset
The PIC16F716 differentiates between various kinds of Reset: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset (during normal operation) WDT Wake-up (during Sleep) Brown-out Reset (BOR)
Note 1:
2:
Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during Sleep and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different Reset situations as indicated in Table 9-4. These bits are used in software to determine the nature of the Reset. See Table 9-6 for a full description of Reset states of all registers.
External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that voltage drop across R does not violate the device's electrical specification. R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
3:
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PIC16F716
9.5 Power-up Timer (PWRT) 9.7
The Power-up Timer provides a fixed nominal time-out, on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. The power-up timer enable Configuration bit, PWRTE, is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See AC parameters for details.
Programmable Brown-Out Reset (PBOR)
The PIC16F716 has on-chip Brown-out Reset circuitry. A Configuration bit, BOREN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. The BORV Configuration bit selects the programmable Brown-out Reset threshold voltage (VBOR). When BORV is 1, VBOR IS 4.0V. When BORV is 0, VBOR is 2.5V A Brown-out Reset occurs when VDD falls below VBOR for a time greater than parameter TBOR (see Table 12-4). A Brown-out Reset is not guaranteed to occur if VDD falls below VBOR for less than parameter TBOR. On any Reset (Power-on, Brown-out, Watchdog, etc.) the chip will remain in Reset until VDD rises above VBOR. The Power-up Timer will be invoked and will keep the chip in Reset an additional 72 ms only if the Power-up Timer enable bit in the Configuration register is set to 0 (PWRTE = 0). If the Power-up Timer is enabled and VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 72 ms Reset. See Figure 9-6. For operations where the desired brown-out voltage is other than 4.0V or 2.5V, an external brown-out circuit must be used. Figure 9-8, Figure 9-9 and Figure 9-10 show examples of external Brown-out Protection circuits.
9.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. See AC parameters for details. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from Sleep.
(c) 2007 Microchip Technology Inc.
DS41206B-page 65
PIC16F716
FIGURE 9-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset MCLR WDT Module VDD rise detect VDD Brown-out Reset OST/PWRT OST 10-bit Ripple counter OSC1 (1) On-chip RC OSC PWRT 10-bit Ripple counter R Q Chip_Reset Sleep WDT Time-out Reset Power-on Reset BOREN S
PWRTE See Table 9-3 for time-out situations. Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
FIGURE 9-6:
BROWN-OUT SITUATIONS (PWRTE = 0)
VDD
VBOR
Internal Reset VDD
72 ms
VBOR <72 ms
Internal Reset
72 ms
VDD
VBOR
Internal Reset
72 ms
DS41206B-page 66
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 9-7:
VDD 33k Q1 10k 40k MCLR PIC16F716 Vss RST
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1
VDD
FIGURE 9-9:
VDD MCP809
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 3
bypass capacitor
VDD
VDD MCLR PIC16F716
Note 1: This circuit will activate Reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage. 2: Internal Brown-out Reset circuitry should be disabled when using this circuit.
Note 1:
FIGURE 9-8:
VDD R1
EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2
VDD Q1 MCLR
This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. The MCP8XX and MCP1XX families of supervisors provide push-pull and open collector outputs with both high and low active Reset pins. There are 7 different trip point selections to accommodate 5V and 3V systems.
R2
40k
PIC16F716
Note 1: This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD x R1 R1 + R2 = 0.7 V
2: Internal Brown-out Reset should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor.
(c) 2007 Microchip Technology Inc.
DS41206B-page 67
PIC16F716
9.8 Time-out Sequence 9.9
On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 9-10, Figure 9-11, and Figure 9-12 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high will begin execution immediately (Figure 9-12). This is useful for testing purposes or to synchronize more than one PIC16F716 device operating in parallel. Table 9-5 shows the Reset conditions for some Special Function Registers, while Table 9-6 shows the Reset conditions for all the registers.
Power Control/STATUS Register (PCON)
The Power Control/STATUS Register, PCON has two bits. Bit 0 is the Brown-out Reset Status bit, BOR. If the BOREN Configuration bit is set, BOR is `1' on Power-on Reset and reset to `0' when a Brown-out condition occurs. BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating that another Brown-out has occurred. If the BOREN Configuration bit is clear, BOR is unknown on Power-on Reset. Bit 1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up or Brown-out PWRTE = 0 72 ms + 1024 TOSC 72 ms PWRTE = 1 1024 TOSC -- Wake-up from Sleep 1024 TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 9-4:
POR 0 0 0 0 1 1 1 1 1 BOR x 1 x x 0 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
TO 1 1 0 x 1 0 0 u 1 PD 1 1 x 0 1 1 0 u 0 Power-on Reset (BOREN = 0) Power-on Reset (BOREN = 1) Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep or interrupt wake-up from Sleep
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PIC16F716
TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset (BOREN = 0) Power-on Reset (BOREN = 1) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from Sleep Note 1: Program Counter 000h 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register 0001 1xxx 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --01 ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as `0'.
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
(c) 2007 Microchip Technology Inc.
DS41206B-page 69
PIC16F716
TABLE 9-6:
Register W INDF TMR0 PCL STATUS FSR PORTA(4), (5), (6) PORTB(4), (5) PCLATH INTCON PIR1 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS ADRES ADCON0 OPTION_REG TRISA TRISB PIE1 PCON PR2 ADCON1
INITIALIZATION CONDITIONS FOR ALL REGISTERS OF THE PIC16F716
Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx --xx 0000 xxxx xxxx ---0 0000 0000 -00x -0-- -000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 -000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 00-0 0000 xxxx xxxx 0000 0000 1111 1111 --11 1111 1111 1111 -0-- -000 ---- --qq 1111 1111 ---- -000 MCLR Resets WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu
(3)
Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu --uu uuuu uuuu uuuu ---u uuuu uuuu -uuu(1) -u-- -uuu(1) uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu -u-- -uuu ---- --uu uuuu uuuu ---- -uuu
uuuu uuuu --xx 0000 uuuu uuuu ---0 0000 0000 -00u -0-- -000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 00-0 0000 uuuu uuuu 0000 0000 1111 1111 --11 1111 1111 1111 -0-- -000 ---- --uu 1111 1111 ---- -000
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 9-5 for Reset value for specific condition. 4: On any device Reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch. 6: Output latches are unknown or unchanged. Analog inputs default to analog and read `0'.
DS41206B-page 70
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 9-10:
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 9-11:
VDD MCLR INTERNAL POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST
FIGURE 9-12:
VDD MCLR INTERNAL POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST
(c) 2007 Microchip Technology Inc.
DS41206B-page 71
PIC16F716
9.10 Interrupts
The PIC16F716 devices have up to 7 sources of interrupt. The Interrupt Control Register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in Special Function Registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in Special Function Register, INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
A Global Interrupt Enable bit, GIE of the INTCON register enables all un-masked interrupts when set, or disables all interrupts when cleared. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on Reset and when an interrupt vector occurs. The "return-from-interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.
FIGURE 9-13:
INTERRUPT LOGIC
T0IF T0IE INTF INTE ADIF ADIE RBIF RBIE PEIE GIE Wake-up (If in Sleep mode)
Interrupt to CPU
CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE
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PIC16F716
9.10.1 INT INTERRUPT
9.11
Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered, either rising if bit INTEDG of the OPTION register is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF of the INTCON register is set. This interrupt can be disabled by clearing enable bit INTE of the INTCON register. Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from Sleep, if bit INTE was set prior to going into Sleep. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.13 "Power-down Mode (Sleep)" for details on Sleep mode.
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in firmware. Example 9-1 stores and restores the W, STATUS, PCLATH and FSR registers. Context storage registers, W_TEMP, STATUS_TEMP, PCLATH_TEMP and FSR_TEMP, must be defined in Common RAM which are those addresses between 70h-7Fh in Bank 0 and between F0h-FFh in Bank 1. The example: a) b) c) d) e) f) Stores the W register. Stores the STATUS register in Bank 0. Stores the PCLATH register. Stores the FSR register. Executes the Interrupt Service Routine code (User-generated). Restores all saved registers in reverse order from which they were stored.
9.10.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF of the INTCON register. The interrupt can be enabled/disabled by setting/clearing enable bit T0IE of the INTCON register. (Section 4.0 "Timer0 Module").
9.10.3
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF of the INTCON register. The interrupt can be enabled/disabled by setting/clearing enable bit RBIE of the INTCON register. (Section 3.2 "PORTB and the TRISB Register").
EXAMPLE 9-1:
MOVWF SWAPF MOVWF MOVF MOVWF CLRF BCF MOVF MOVWF : :(ISR) : MOVF MOVWF MOVF MOVWF SWAPF MOVWF SWAPF SWAPF RETFIE
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
W_TEMP STATUS,W STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH STATUS, IRP FSR, W FSR_TEMP ;Copy W to TEMP register, could be bank one or zero ;Swap status to be saved into W ;Save status to bank zero STATUS_TEMP register ;Only required if using pages 1, 2 and/or 3 ;Save PCLATH into W ;Page zero, regardless of current page ;Return to Bank 0 ;Copy FSR to W ;Copy FSR from W to FSR_TEMP
FSR_TEMP,W FSR PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W
;Restore FSR ;Move W into FSR ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W ;Return from interrupt and enable GIE
(c) 2007 Microchip Technology Inc.
DS41206B-page 73
PIC16F716
9.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip, RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device have been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset). If the device is in Sleep mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing Configuration bit WDTE (Section 9.1 "Configuration Bits"). WDT time-out period values may be found in the Electrical Specifications section under TWDT (parameter #31). Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION register. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset condition.
. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 9-14:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 4-1) 0 WDT Timer 1 M U X Postscaler 8 8-to-1 MUX WDT Enable Bit PSA To TMR0 (Figure 4-1) PS2:PS0
0 MUX
1 PSA
WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 9-7:
Name CONFIG1(1) OPTION_REG Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7 BORV RBPU Bit 6 BOREN INTEDG Bit 5 -- T0CS Bit 4 -- T0SE Bit 3 PWRTE PSA Bit 2 WDTE PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0 Value on POR, BOR -- 1111 1111 Value on all other Resets -- 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used the Watchdog Timer. See Configuration Word Register (Register 9-1) for operation of all register bits.
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9.13 Power-down Mode (Sleep)
Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit of the STATUS register is cleared, the TO of the STATUS register bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low or high-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and the disable external clocks. Pull all I/O pins that are high-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (parameter D042). The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. ECCP capture mode interrupt. ADC running in ADRC mode.
Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
9.13.1
WAKE-UP FROM SLEEP
9.13.2
WAKE-UP USING INTERRUPTS
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or some peripheral interrupts.
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
External MCLR Reset will cause a device Reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up).
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FIGURE 9-15:
OSC1 CLKOUT(4) INT pin INTF flag (INTCON Reg.) GIE bit (INTCON Reg.) INSTRUCTION FLOW PC PC PC+1 Inst(PC + 1) Sleep PC+2 PC+2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Instruction fetched Inst(PC) = Sleep Instruction executed Inst(PC - 1) Note 1: 2: 3: 4: Processor in Sleep Interrupt Latency (Note 3) TOST(2)
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
XT, HS or LP Oscillator mode assumed. TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC Osc mode. GIE = 1 assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
9.14
Program Verification/Code Protection
9.16
In-Circuit Serial ProgrammingTM
If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes.
9.15
ID Locations
Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the 4 Least Significant bits of the ID location are used.
PIC16F716 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details on serial programming, please refer to the In-Circuit Serial ProgrammingTM (ICSPTM) Specification, (DS40245).
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10.0 INSTRUCTION SET SUMMARY
TABLE 10-1:
Field
f W b k x
The PIC16F716 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 10-1, while the various opcode fields are summarized in Table 10-1. Table 10-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an 8-bit or 11-bit constant, or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
d
PC TO C DC Z PD
FIGURE 10-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
10.1
Read-Modify-Write Operations
0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register. For example, a CLRF PORTA instruction will read PORTA, clear all the data bits, then write the result back to PORTA. This example would have the unintended consequence of clearing the condition that set the RAIF flag.
0
k = 11-bit immediate value
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TABLE 10-2:
Mnemonic, Operands
PIC16F716 INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C, DC, Z Z Z Z Z Z Z Z Z 1, 2 1, 2 2 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2
C C C, DC, Z Z
1, 2 1, 2 1, 2 1, 2 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, b f, b f, b f, b k k k - k k k - k - - k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C, DC, Z Z TO, PD Z 1, 2 1, 2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO, PD C, DC, Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
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10.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a two-cycle instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a two-cycle instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1
MOVF FSR, 0
MOVWF Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVW F OPTION MOVWF f 0 f 127
Words: Cycles: Example:
Before Instruction OPTION = W = After Instruction OPTION = W =
0xFF 0x4F 0x4F 0x4F
After Instruction W= value in FSR register Z=1
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1
MOVLW 0x5A
NOP Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation [ label ] None No operation None No operation. 1 1
NOP
MOVLW k
NOP
0 k 255
Words: Cycles: Example:
After Instruction W=
0x5A
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RETFIE Syntax: Operands: Operation: Status Affected: Description: Return from Interrupt [ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2
RETFIE
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table
;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table
RETFIE
Words: Cycles: Example:
Words: Cycles: Example:
After Interrupt PC = GIE =
TABLE TOS 1
Before Instruction W = 0x07 After Instruction W = value of k8
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation:
Enter Sleep mode [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
RLF
f,d
Status Affected: Description:
Words: Cycles: Example:
1 1
RLF REG1,0 REG1 C = = = = = 1110 0110 0 1110 0110 1100 1100 1
Before Instruction After Instruction
REG1 W C
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBLW Syntax: Operands: Operation: Description:
Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. C=0 C=1 DC = 0 DC = 1 W>k Wk W<3:0> > k<3:0> W<3:0> k<3:0>
Status Affected: C, DC, Z
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SUBWF Syntax: Operands: Operation: Description: Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f. C=0 C=1 DC = 0 DC = 1 W>f Wf W<3:0> > f<3:0> W<3:0> f<3:0> XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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NOTES:
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11.0 DEVELOPMENT SUPPORT
11.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
(c) 2007 Microchip Technology Inc.
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PIC16F716
11.2 MPASM Assembler 11.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
11.6
MPLAB SIM Software Simulator
11.3
MPLAB C18 and MPLAB C30 C Compilers
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
11.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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11.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 11.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
11.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
11.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
(c) 2007 Microchip Technology Inc.
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PIC16F716
11.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
11.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
11.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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PIC16F716
12.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings() Ambient temperature under bias......................................................................................................... .-55C to +125C Storage temperature ........................................................................................................................... -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3V to (VDD +0.3V) Voltage on VDD with respect to VSS ...................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ...................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................ 0V to +8.5V Total power dissipation (Note 1) (PDIP and SOIC)................................................................................................ 1.0W Total power dissipation (Note 1) (SSOP) ............................................................................................................. 0.65W Maximum current out of VSS pin ........................................................................................................................ 300 mA Maximum current into VDD pin ........................................................................................................................... 250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................20 mA Maximum output current sunk by any I/O pin....................................................................................................... 25 mA Maximum output current sourced by any I/O pin ................................................................................................. 25 mA Maximum current sunk by PORTA and PORTB (combined).............................................................................. 200 mA Maximum current sourced by PORTA and PORTB (combined) ........................................................................ 200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
(c) 2007 Microchip Technology Inc.
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PIC16F716
FIGURE 12-1:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 10 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 20 25
PIC16F716 VOLTAGE-FREQUENCY GRAPH, -40C < TA < +85C(1)
FIGURE 12-2:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0
PIC16F716 VOLTAGE-FREQUENCY GRAPH, 85C < TA < +125C(1)
4
10 Frequency (MHz)
20
25
Note 1:
The shaded region indicates the permissible combinations of voltage and frequency.
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PIC16F716
12.1 DC Characteristics: PIC16F716 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
DC CHARACTERISTICS Param No. D001 D001A D002* D003 D004* D005 VDR RAM Data Retention Voltage(1)
Sym VDD
Characteristic Supply Voltage
2.0 3.0 -- -- 0.05
-- -- 1.5* Vss --
5.5 5.5 -- -- --
V V V V
Industrial Extended
VPOR VDD Start Voltage to ensure internal Power-on Reset signal SVDD VDD Rise Rate to ensure internal Power-on Reset signal VBOR Brown-out Reset voltage trip point
See section on Power-on Reset for details
V/ms PWRT enabled (PWRTE bit clear)
3.65 2.2
4.0 2.5
4.35 2.7
V V
BOREN bit set, BOR bit = `1' BOREN bit set, BOR bit = `0'
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered without losing RAM data.
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PIC16F716
12.2 DC Characteristics: PIC16F716 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C Min Typ Max Units VDD Conditions DC CHARACTERISTICS Param No. D001 IDD D010 Supply Current -- -- -- -- D011 -- -- -- D012 -- -- -- D013 IPD D020 Power-down Base Current -- -- -- Peripheral Module Current D021
(1)
Sym VDD
Characteristic Supply Voltage
2.0
-- 14 23 45 120 180 290 220 350 600 2.1 2.5 0.1 0.1 0.2 1 2 9 37 40 45 1.8 2.6 3.0
5.5 17 28 63.7 160 250 370 300 470 780 2.9 3.3 0.8 0.85 2.7 2.0 3.5 13.5 50 55 60 6 7.5 9
V A A A A A A A A A mA mA A A A A A A A A A A A A
-- 2.0 3.0 5.0 2.0 3.0 5.0 2.0 3.0 5.0 4.5 5.0 2.0 3.0 5.0 2.0 3.0 5.0 3.0 4.5 5.0 2.0 3.0 5.0 T1OSC Current BOR Current WDT Current FOSC = 20 MHz HS Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 32 kHz LP Oscillator mode
--
WDT, BOR and T1OSC: disabled
-- -- -- -- D022 -- -- D025 -- -- --
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral "" current can be determined by subtracting the base IDD or IPD current from this limit.
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PIC16F716
12.3 DC Characteristics: PIC16F716 (Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Min Typ Max Units VDD Conditions DC CHARACTERISTICS Param No. D001 IDD D010E Supply Current -- -- -- D011E D012E D013E IPD D020E Peripheral Module Current D021E
(1)
Sym VDD
Characteristic Supply Voltage
3.0
-- 21 38 182 293 371 668 2.6 3 0.1 0.2 2 9 37 40 45 2.6 3.0
5.5 28 63.7 250 370 470 780 2.9 3.3 11 15 19 22 60 71 76 20 25
V A A A A A A mA mA A A A A A A A A A
-- 3.0 5.0 3.0 5.0 3.0 5.0 4.5 5.0 3.0 5.0 3.0 5.0 3.0 4.5 5.0 3.0 5.0 T1OSC Current BOR Current WDT Current FOSC = 32 kHz LP Oscillator mode FOSC = 1 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode FOSC = 20 MHz HS Oscillator mode
-- -- -- -- -- Power-down Base Current -- -- -- -- -- -- -- --
WDT, BOR and T1OSC: disabled
D022E
D025E
--
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral "" current can be determined by subtracting the base IDD or IPD current from this limit.
(c) 2007 Microchip Technology Inc.
DS41206B-page 95
PIC16F716
12.4 DC Characteristics: PIC16F716 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 12.1 "DC Characteristics: PIC16F716 (Industrial, Extended)" and Section 12.4 "DC Characteristics: PIC16F716 (Industrial, Extended)". Characteristic Input Low Voltage I/O ports with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in HS mode) OSC1 (in XT and LP modes) Input High Voltage I/O ports with TTL buffer Min Typ Max Units Conditions
DC CHARACTERISTICS
Param No.
Sym
VIL D030 D030A D031 D032 D033
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 250 -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.6
V V V V V V
4.5V VDD 5.5V otherwise
(Note1)
VIH D040 D040A D041 D042 D042A D043 D060 IIL
with Schmitt Trigger buffer MCLR OSC1 (XT, HS and LP modes) OSC1 (in RC mode) Input Leakage Current(2), (3) I/O ports
2.0 0.25 VDD + 0.8V 0.8 VDD 0.8 VDD 0.7 VDD 0.9 VDD -- --
VDD VDD VDD VDD VDD VDD 1 500 5 5 400 0.6 0.6 0.6 0.6
V V V V V V
4.5V VDD 5.5V otherwise For entire VDD range (Note1)
A
nA
D061 D063 D070 D080 IPURB VOL
MCLR, RA4/T0CKI OSC1/CLKIN PORTB weak pull-up current Output Low Voltage I/O ports
-- -- 50 -- --
A A A
V V V V
Vss VPIN VDD, Pin at high-impedance Vss VPIN VDD, Pin configured as analog input Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc modes VDD = 5V, VPIN = VSS IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1.
D083
OSC2/CLKOUT (RC Osc mode)
-- --
Output High Voltage D090 VOH I/O ports(3) VDD-0.7 VDD-0.7 D092 OSC2/CLKOUT (RC Osc mode) VDD-0.7 VDD-0.7 D150* D100 D101 VOD Open-Drain High Voltage -- -- -- -- -- -- -- -- -- -- -- 8.5 15 V V V V V pF
Capacitive Loading Specs on Output Pins COSC2 OSC2/CLKOUT pin --
Note
* 1:
CIO All I/O pins and OSC2 (in RC mode) -- -- 50 pF These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC Oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC(R) be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
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PIC16F716
12.5
12.5.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
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PIC16F716
12.5.2 TIMING CONDITIONS
The temperature and voltages specified in Table 12-1 apply to all timing specifications, unless otherwise noted. Figure 12-3 specifies the load conditions for the timing specifications.
TABLE 12-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 12.1 "DC Characteristics: PIC16F716 (Industrial, Extended)" and Section 12.4 "DC Characteristics: PIC16F716 (Industrial, Extended)". LC parts operate for commercial/industrial temp's only.
AC CHARACTERISTICS
FIGURE 12-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 VDD/2 Rl Pin VSS Pin VSS Cl Legend: RL = 464 CL = 50 pF for all pins except OSC2/CLKOUT 15 pF for OSC2 output Cl Load condition 2
12.5.3
TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 12-4:
OSC1 1 2 CLKOUT 3 3 4 4
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PIC16F716
TABLE 12-2:
Param No. 1A Sym FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic Ext. Clock Input Frequency(1) Min Typ Max Units Conditions
DC -- 4 MHz RC and XT Osc modes DC -- 20 MHz HS Osc mode DC -- 200 kHz LP Osc mode (1) Oscillator Frequency DC -- 4 MHz RC Osc mode 0.1 -- 4 MHz XT Osc mode 4 -- 20 MHz HS Osc mode 5 -- 200 kHz LP Osc mode 1 TOSC External CLKIN Period(1) 250 -- -- ns RC and XT Osc modes 50 -- -- ns HS Osc mode 5 -- -- s LP Osc mode Oscillator Period(1) 250 -- -- ns RC Osc mode 250 -- 10,000 ns XT Osc mode 50 -- 250 ns HS Osc mode 5 -- -- s LP Osc mode 2 Tcy Instruction Cycle Time(1) 200 -- DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 -- -- ns XT oscillator TosH Low Time 2.5 -- -- s LP oscillator 15 -- -- ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or -- -- 25 ns XT oscillator TosF Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max" cycle time limit is "DC" (no clock) for all devices.
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PIC16F716
FIGURE 12-5:
OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 15 new value 19 18 12 16 11
CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
Note 1:
Refer to Figure 12-3 for load conditions.
TABLE 12-3:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* 18A* 19* 20* 20A* 21* 21A* 22* 23* TINP TRBP TIOF
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port input valid before CLKOUT Port input hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port Standard input invalid (I/O in hold Extended (LC) time) Port input valid to OSC1 (I/O in setup time) Port output rise time Port output fall time INT pin high or low time RB<7:4> change INT high or low time Standard Extended (LC) Standard Extended (LC) Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- Tcy Tcy Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 20 -- -- 150 -- -- -- 40 80 40 80 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
Sym TOSH2CKL TCKR TCKF TCKL2IOV TIOV2CKH TCKH2IOI TOSH2IOV TOSH2IOI
TOSH2CKH OSC1 to CLKOUT
TIOV2OSH TIOR
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edge. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
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PIC16F716
FIGURE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING(1)
VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins 33 32 30
31
34
Note 1:
Refer to Figure 12-3 for load conditions.
FIGURE 12-7:
BROWN-OUT RESET TIMING
VDD
BVDD 35
TABLE 12-4:
Param No. 30 31* 32 33* 34 35 Sym TMCL TWDT TOST TPWRT TIOZ TBOR
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O high-impedance from MCLR Low or WDT Reset Brown-out Reset Pulse Width Min 2 7 TBD -- 28 TBD -- 100 Typ -- 18 TBD 1024 TOSC 72 TBD -- -- Max Units -- 33 TBD -- 132 TBD 2.1 -- s ms ms -- ms ms s s VDD BVDD (D005) Conditions VDD = 5V, -40C to +125C VDD = 5V, -40C to +85C VDD = 5V, +85C to +125C TOSC = OSC1 period VDD = 5V, -40C to +85C VDD = 5V, +85C to +125C
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2007 Microchip Technology Inc.
DS41206B-page 101
PIC16F716
FIGURE 12-8:
T0CKI 40 42 T1OSO/T1CKI 45 47 TMR0 or TMR1 Note 1: Refer to Figure 12-3 for load conditions. 46 48 41
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS(1)
TABLE 12-5:
Param No. 40* 41* 42* Sym Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units ns ns ns ns ns ns Conditions Must also meet parameter 42 Must also meet parameter 42 N = prescale value (2, 4,..., 256) Must also meet parameter 47
45*
Tt1H
46*
Tt1L
47*
Tt1P
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Standard Prescaler = 2,4,8 Asynchronous Standard T1CKI Low Time Synchronous, Prescaler = 1 Synchronous, Standard Prescaler = 2,4,8 Asynchronous Standard T1CKI input Synchronous Standard period
-- --
-- --
ns ns
30 0.5TCY + 20 15
-- -- --
-- -- --
ns ns ns
Must also meet parameter 47
48*
Asynchronous Standard -- -- ns Timer1 oscillator input frequency range -- 32.768 kHz (oscillator enabled by setting bit T1OSCEN) TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc -- 7Tosc -- * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Ft1
30 Greater of: 30 OR TCY + 40 N 60 32.768
-- --
-- --
ns ns
N = prescale value (1, 2, 4, 8)
DS41206B-page 102
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 12-9: CAPTURE/COMPARE/PWM TIMINGS(1)
CCP1 (Capture Mode)
50 52
51
CCP1 (Compare or PWM Mode) 53 Note 1: Refer to Figure 12-3 for load conditions. 54
TABLE 12-6:
Param Sym No. 50* 51* 52*
CAPTURE/COMPARE/PWM REQUIREMENTS
Characteristic No Prescaler With Prescaler Standard Min 0.5TCY + 20 10 0.5TCY + 20 10 3TCY + 40 N Standard Extended Standard Extended -- -- -- -- Typ Max Units -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns N = prescale value (1,4, or 16) Conditions
TccL CCP1 input low time
TccH CCP1 input high No Prescaler time With Prescaler Standard TccP CCP1 input period
53* 53A* 54* 54A*
TccR CCP1 output rise time TccF CCP1 output fall time
10 -- 10 --
40 80 40 80
ns ns ns ns
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2007 Microchip Technology Inc.
DS41206B-page 103
PIC16F716
TABLE 12-7:
Param Sym No. A00 A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 NR
A/D CONVERTER CHARACTERISTICS: PIC16F716 (INDUSTRIAL, EXTENDED)
Characteristic Min 2.5 -- -- -- -- -- -- -- 2.5V VSS 0.3 -- -- Typ -- -- -- -- -- -- -- guaranteed(3) -- -- -- 180 Max 5.5 8-bits <1 <1 <1 <1 <1 -- VDD + 0.3 VREF + 0.3 10.0 -- Units V bit VREF = VDD = 5.12V, VSS VAIN VREF Conditions
VDD VDD Operation Resolution
EABS Total Absolute error EIL EDL EFS Integral linearity error Differential linearity error Full scale error
LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD= 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF -- V V k A Average current consumption when A/D is on.(1) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 12.1 "DC Characteristics: PIC16F716 (Industrial, Extended)". During A/D Conversion cycle VSS VAIN VREF
EOFF Offset error -- Monotonicity
VREF Reference voltage VAIN Analog input voltage ZAIN Recommended impedance of analog voltage source IAD A/D conversion current (VDD) Standard
A50
IREF VREF input current(2)
10
--
1000
A
--
--
10
A
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
DS41206B-page 104
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 12-10: A/D CONVERSION TIMING
1 Tcy (TOSC/2)(1) 131 130 A/D CLK 132
BSF ADCON0, GO 134 Q4
A/D DATA
7
6
5
4
3
2
1
0
ADRES ADIF GO SAMPLE
OLD_DATA
NEW_DATA
DONE SAMPLING STOPPED
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 12-8:
Param No. 130 Sym TAD
A/D CONVERSION REQUIREMENTS
Characteristic A/D clock period Industrial Industrial Extended Extended Min 1.6 1.6 1.6 1.6 9.5 (Note 2) 5* Typ -- 4.0 -- 6.0 -- 20 -- Max -- 6.0 -- 9.0 9.5 -- -- Units s s s s TAD s s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V A/D RC mode TOSC based, VREF 3.0V A/D RC mode
131 132
TCNV Conversion time (not including S/H time)(1) TACQ Acquisition time
134
TGO
Q4 to A/D clock start
--
TOSC/2 **
--
--
135
TSWC Switching from convert sample time
1.5 **
--
--
TAD
* These parameters are characterized but not tested. ** This specification ensured by design. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 12.1 "DC Characteristics: PIC16F716 (Industrial, Extended)" for min. conditions.
(c) 2007 Microchip Technology Inc.
DS41206B-page 105
PIC16F716
NOTES:
DS41206B-page 106
(c) 2007 Microchip Technology Inc.
PIC16F716
13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. FIGURE 13-1:
3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
3.0
5.5V 5.0V
2.5
IDD (mA)
2.0
4.0V
1.5
3.0V
1.0
2.0V
0.5
0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz FOSC 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz
(c) 2007 Microchip Technology Inc.
DS41206B-page 107
PIC16F716
FIGURE 13-2:
4.0 3.5 3.0 2.5 IDD (mA) 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz FOSC 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz 3.0V 2.0V Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) 5.5V 5.0V
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode
4.0V
FIGURE 13-3:
4.0 3.5 3.0 2.5 IDD (mA) 2.0 1.5 1.0 0.5 0.0
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
Typical IDD vs. FOSC Over Vdd HS Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
5.5V 5.0V 4.5V
4.0V 3.5V 3.0V
4 MHz
10 MHz FOSC
16 MHz
20 MHz
DS41206B-page 108
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 13-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
Maximum IDD vs. FOSC Over Vdd HS Mode 5.0 4.5 4.0 3.5 IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4 MHz 10 MHz FOSC 16 MHz 20 MHz 4.0V 3.5V 3.0V Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) 5.5V 5.0V 4.5V
FIGURE 13-5:
900 800 700 600 IDD (A) 500 400 300
TYPICAL IDD vs. VDD OVER FOSC (XT MODE)
XT Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
4 MHz
1 MHz 200 100 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41206B-page 109
PIC16F716
FIGURE 13-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)
XT Mode 1,400 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
1,200
1,000
IDD (A)
800 4 MHz 600
400
1 MHz
200
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 13-7:
800 700 600 500 IDD (A) 400 300
TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
4 MHz
1 MHz 200 100 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41206B-page 110
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 13-8:
1,400 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
MAXIMUM IDD vs. VDD (EXTRC MODE)
EXTRC Mode
1,200
1,000 4 MHz
IDD (A)
800
600
400
1 MHz
200
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 13-9:
70
IDD vs. VDD (LP MODE)
60
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
50 32 kHz Maximum
IDD (A)
40
30
20
32 kHz Typical
10
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41206B-page 111
PIC16F716
FIGURE 13-10:
0.45 0.40 0.35 0.30 IPD (A) 0.25 0.20 0.15 0.10 0.05 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Typical (Sleep Mode all Peripherals Disabled)
FIGURE 13-11:
18.0 16.0 14.0
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Maximum (Sleep Mode all Peripherals Disabled)
Typical: Statistical Mean @25C Maximum: Mean + 3 Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) Max. 125C
12.0 IPD (A) 10.0 8.0 6.0 4.0 Max. 85C 2.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41206B-page 112
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 13-12:
160 140 120 100 IPD (A) 80 Maximum 60 40 20 0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
BOR IPD vs. VDD OVER TEMPERATURE
Typical
FIGURE 13-13:
3.0
TYPICAL WDT IPD vs. VDD OVER TEMPERATURE
Typical
2.5
Typical: Statistical Mean @25C Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
2.0 IPD (A)
1.5
1.0
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41206B-page 113
PIC16F716
FIGURE 13-14:
25.0
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
Maximum
20.0 Max. 125C 15.0 Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
IPD (A)
10.0
5.0
Max. 85C
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 13-15:
30 28 26 24 22 Time (ms) 20
WDT PERIOD vs. VDD OVER TEMPERATURE
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) Max. (125C) Max. (85C)
Typical 18 16 14 12 10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
Minimum
DS41206B-page 114
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 13-16:
30 28 26 Maximum 24 22 Time (ms) 20 Typical 18 16 Minimum 14 12 10 -40C 25C Temperature (C) 85C 125C Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V)
Vdd = 5V
(c) 2007 Microchip Technology Inc.
DS41206B-page 115
PIC16F716
FIGURE 13-17: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40xC TO 125xC)
0.8 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
0.7
Max. 125C
0.6
0.5 VOL (V)
Max. 85C
0.4 Typical 25C
0.3
0.2 Min. -40C 0.1
0.0 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
FIGURE 13-18:
0.45 0.40 0.35
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
Typical: Statistical Mean @25C Typical: Statistical Mean @25xC Maximum: Mean (Worst-case Temp) + 3 Maximum: Means + 3 to 125xC) (-40xC (-40C to 125C)
Max. 125C Max. 85C
0.30 0.25 Typ. 25C 0.20 0.15 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 IOL (mA) 8.0 8.5 9.0 9.5 10.0
VOL (V)
Min. -40C
DS41206B-page 116
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 13-19:
3.5
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.0
Max. -40C Typ. 25C
2.5
Min. 125C 2.0 VOH (V)
1.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
1.0
0.5
0.0 0.0 -0.5 -1.0 -1.5 -2.0 IOH (mA) -2.5 -3.0 -3.5 -4.0
FIGURE 13-20:
5.5
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) ( , )
5.0 Max. -40C
Typ. 25C 4.5 VOH (V) Min. 125C
4.0
3.5
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 IOH (mA) -3.0 -3.5 -4.0 -4.5 -5.0
(c) 2007 Microchip Technology Inc.
DS41206B-page 117
PIC16F716
FIGURE 13-21:
1.7 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C) Max. -40C
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(TTL Input, -40xC TO 125xC)
1.5
1.3 VIN (V)
Typ. 25C 1.1 Min. 125C 0.9
0.7
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 13-22:
4.0
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
(ST Input, -40xC TO 125xC)
VIH Max. 125C 3.5 Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
VIH Min. -40C
3.0
VIN (V)
2.5
2.0 VIL Max. -40C 1.5 VIL Min. 125C
1.0
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS41206B-page 118
(c) 2007 Microchip Technology Inc.
PIC16F716
FIGURE 13-23:
45.0 40.0 35.0 30.0 IPD (mA) 25.0 20.0 15.0 10.0 5.0 0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 Max. 85C Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 Maximum: Mean + 3 to 125xC) (-40xC (-40C to 125C) Max. 125C
T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)
Typ. 25C
FIGURE 13-24:
8
ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE
125C 6
Typical: Statistical Mean @25C Maximum: Mean (Worst-case Temp) + 3 (-40C to 125C)
85C
Time (s)
4
25C
-40C 2
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS41206B-page 119
PIC16F716
NOTES:
DS41206B-page 120
(c) 2007 Microchip Technology Inc.
PIC16F716
14.0
14.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F716-04/P e3 0610017
18-Lead SOIC (7.50 mm)
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16F716-20 /SO e3 0610017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC16F716 -20I/SS025 0610017
Legend: XX...X Y YY WW NNN
e3
* Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PIC(R) device marking consists of Microchip part number, year code, week code, and traceability code. For PIC(R) device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
(c) 2007 Microchip Technology Inc.
DS41206B-page 121
PIC16F716
14.2 Package Details
The following sections give the technical details of the packages.
18-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1
E1
1
2
3 D E
A
A2 L A1 b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .300 .240 .880 .115 .008 .045 .014 - MIN INCHES NOM 18 .100 BSC - .130 - .310 .250 .900 .130 .010 .060 .018 - .210 .195 - .325 .280 .920 .150 .014 .070 .022 MAX
c
eB
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-007B
DS41206B-page 122
(c) 2007 Microchip Technology Inc.
PIC16F716
18-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 1 23 b
e h A2 c h
A
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.20 0.31 5 5 0.25 0.40 - 2.05 0.10 MIN
MILLIMETERS NOM 18 1.27 BSC - - - 10.30 BSC 7.50 BSC 11.55 BSC - - 1.40 REF - - - - - 8 0.33 0.51 15 0.75 1.27 2.65 - 0.30 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-051B
(c) 2007 Microchip Technology Inc.
DS41206B-page 123
PIC16F716
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 12 b e
A
A2
c
A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 6.90 0.55 MIN MILLIMETERS NOM 20 0.65 BSC - 1.75 - 7.80 5.30 7.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 7.50 0.95 MAX
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B
DS41206B-page 124
(c) 2007 Microchip Technology Inc.
PIC16F716
APPENDIX A: REVISION HISTORY APPENDIX B:
Revision A (June 2003) Original data sheet. However, the device described in this data sheet are upgrades to PIC16C716. Revision B (February 2007) Updated with current formats and added Characterization Data. Replaced Package Drawings.
CONVERSION CONSIDERATIONS
This is a Flash program memory version of the PIC16C716 device. Refer to the migration document, DS40059, for more information about differences between the PIC16F716 and PIC16C716.
(c) 2007 Microchip Technology Inc.
DS41206B-page 125
PIC16F716
APPENDIX C: MIGRATION FROM BASE-LINE TO MID-RANGE DEVICES
To convert code written for PIC16C5X to PIC16F716, the user should take the following steps: 1. 2. Remove any program memory page select operations (PA2, PA1, PA0 bits) for CALL, GOTO. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme. Eliminate any data memory page switching. Redefine data variables to reallocate them. Verify all writes to STATUS, OPTION, and FSR registers since these have changed. Change Reset vector to 0000h Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. 2: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required.
This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to a mid-range device (i.e., PIC16F716). The following are the list of modifications over the PIC16C5X microcontroller family: 1. Instruction word length is increased to 14-bits. This allows larger page sizes both in program memory (2K now as opposed to 512 before) and register file (128 bytes now versus 32 bytes before). A PC high latch register (PCLATH) is added to handle program memory paging. Bits PA2, PA1, PA0 are removed from STATUS register. Data memory paging is redefined slightly. STATUS register is modified. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compatibility with PIC16C5X. OPTION_REG and TRIS registers are made addressable. Interrupt capability is added. Interrupt vector is at 0004h. Stack size is increased to 8 deep. Reset vector is changed to 0000h. Reset of all registers is revisited. Five different Reset (and wake-up) types are recognized. Registers are reset differently. Wake-up from Sleep through interrupt is added. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These timers are invoked selectively to avoid unnecessary delays on power-up and wake-up. PORTB has weak pull-ups and interrupt-onchange feature. T0CKI pin is also a port pin (RA4) now. FSR is made a full eight-bit register. "In-circuit serial programming" is made possible. The user can program PIC16F716 devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). PCON STATUS register is added with a Poweron Reset Status bit (POR). Brown-out protection circuitry has been added. Controlled by Configuration Word bits BOREN and BORV. Brown-out Reset ensures the device is placed in a Reset condition if VDD dips below a fixed setpoint.
3. 4. 5. .
2.
3. 4.
5. 6. 7. 8. 9.
10. 11.
12. 13. 14. 15.
16. 17.
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(c) 2007 Microchip Technology Inc.
PIC16F716
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PIC16F716
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F716 Questions: 1. What are the best features of this document? Y N Literature Number: DS41206B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
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INDEX
A
A/D ADCON0 Register......................................................... 9 ADCON1 Register....................................................... 10 ADRES Register ........................................................... 9 Converter Characteristics ......................................... 104 Timing Diagram......................................................... 105 Absolute Maximum Ratings ................................................ 91 ADC .................................................................................... 37 Acquisition Requirements ........................................... 43 Associated registers.................................................... 45 Block Diagram............................................................. 37 Calculating Acquisition Time....................................... 43 Channel Selection....................................................... 38 Configuration............................................................... 38 Configuring Interrupt ................................................... 40 Conversion Clock........................................................ 38 Conversion Procedure ................................................ 40 Internal Sampling Switch (RSS) IMPEDANCE ................ 43 Interrupts..................................................................... 39 Operation .................................................................... 40 Operation During Sleep .............................................. 40 Port Configuration ....................................................... 38 Reference Voltage (VREF)........................................... 38 Source Impedance...................................................... 43 Special Event Trigger.................................................. 40 ADCON0 Register........................................................... 9, 41 ADCON1 Register......................................................... 10, 42 ADRES Register ................................................................... 9 Analog-to-Digital Converter. See ADC Assembler MPASM Assembler..................................................... 88
C
C Compilers MPLAB C18................................................................ 88 MPLAB C30................................................................ 88 Capture Module. See Enhanced Capture/Compare/ PWM(ECCP) Capture/Compare/PWM (CCP) Associated registers w/ Capture................................. 49 Associated registers w/ Compare............................... 51 Associated registers w/ PWM..................................... 60 Capture Mode............................................................. 48 CCP1 Pin Configuration ............................................. 48 CCP1CON Register...................................................... 9 CCPR1H Register ........................................................ 9 CCPR1L Register ......................................................... 9 Compare Mode........................................................... 50 CCP1 Pin Configuration ..................................... 50 Software Interrupt Mode ............................... 48, 50 Special Event Trigger ......................................... 50 Timer1 Mode Selection................................. 48, 50 Flag (CCP1IF Bit) ....................................................... 15 Prescaler .................................................................... 48 PWM Mode................................................................. 52 Duty Cycle .......................................................... 53 Effects of Reset .................................................. 55 Example PWM Frequencies and Resolutions, 20 MHZ...................................................... 54 Example PWM Frequencies and Resolutions, 8 MHz ........................................................ 54 Operation in Sleep Mode.................................... 55 Setup for Operation ............................................ 55 System Clock Frequency Changes .................... 55 PWM Period ............................................................... 53 Setup for PWM Operation .......................................... 55 Timing Diagram ........................................................ 103 CCP1CON (Enhanced) Register ........................................ 47 Code Examples Assigning Prescaler to Timer0.................................... 28 Assigning Prescaler to WDT....................................... 28 Changing Between Capture Prescalers ..................... 48 How to Clear RAM Using Indirect Addressing............ 18 Initializing PORTA ...................................................... 19 Initializing PORTB ...................................................... 21 Code Protection ............................................................ 61, 76 Compare Module. See Enhanced Capture/ Compare/PWM (ECCP) CONFIG Register ............................................................... 62 Configuration Bits ............................................................... 61 Conversion Considerations............................................... 125 Customer Change Notification Service............................. 127 Customer Notification Service .......................................... 127 Customer Support............................................................. 127
B
Banking, Data Memory ......................................................... 7 Block Diagrams (CCP) Capture Mode Operation ................................. 48 ADC ............................................................................ 37 ADC Transfer Function ............................................... 44 Analog Input Model ..................................................... 44 Auto-Shutdown ........................................................... 56 CCP PWM................................................................... 52 Compare ..................................................................... 50 Interrupt Sources ........................................................ 72 On-Chip Reset Circuit ................................................. 66 PIC16F716.................................................................... 5 PORTA.................................................................. 19, 20 PORTB........................................................................ 21 RB1/T1OSO/T1CKI..................................................... 22 RB2/T1OSI.................................................................. 22 RB3/CCP1/P1A........................................................... 23 RB4 ............................................................................. 23 RB5 ............................................................................. 24 RB6/P1C ..................................................................... 24 RB7/P1D ..................................................................... 25 Timer1......................................................................... 29 Timer2......................................................................... 35 TMR0/WDT Prescaler................................................. 27 Watchdog Timer (WDT) .............................................. 74 BOR. See Brown-out Reset Brown-out Reset (BOR) .............................. 61, 64, 65, 69, 70 Timing Diagram......................................................... 101
D
Data Memory ........................................................................ 7 Bank Select (RP Bits) ................................................... 7 General Purpose Registers .......................................... 8 Register File Map ......................................................... 8 Special Function Registers........................................... 9 DC Characteristics............................................ 93, 94, 95, 96 Development Support ......................................................... 87 Direct Addressing ............................................................... 18
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E
ECCP. See Enhanced Capture/Compare/PWM ECCPAS Register ............................................................... 57 Effects of Reset PWM mode ................................................................. 55 Electrical Characteristics..................................................... 91 Enhanced Capture/Compare/PWM..................................... 47 Enhanced Capture/Compare/PWM (ECCP) Enhanced PWM Mode Auto-Restart........................................................ 58 Auto-shutdown .................................................... 56 Half-Bridge Application Examples....................... 59 Programmable Dead Band Delay ....................... 59 Shoot-through Current ........................................ 59 Timer Resources......................................................... 47 Errata .................................................................................... 4 External Power-on Reset Circuit ......................................... 64 XORWF ...................................................................... 85 Summary Table .......................................................... 78 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register............................................................ 9, 13 Internal Sampling Switch (RSS) IMPEDANCE ........................ 43 Internet Address ............................................................... 127 Interrupt Sources .......................................................... 61, 72 Interrupt-on-Change (RB) ........................................... 21 RB0/INT Pin, External................................................. 73 TMR0 Overflow........................................................... 73 Interrupts ADC ............................................................................ 40 TMR1 .......................................................................... 30 Interrupts, Context Saving During....................................... 73 Interrupts, Enable Bits Global Interrupt Enable (GIE Bit) ................................ 72 Interrupt-on-Change (RB) Enable (RBIE Bit).............. 73 Interrupts, Flag Bits CCP1 Flag (CCP1IF Bit)............................................. 15 Interrupt-on-Change (RB) Flag (RBIF Bit) .................. 73 TMR0 Overflow Flag (T0IF Bit)................................... 73
F
Firmware Instructions.......................................................... 77 Fuses. See Configuration Bits
I
I/O Ports .............................................................................. 19 ID Locations .................................................................. 61, 76 In-Circuit Serial Programming (ICSP) ........................... 61, 76 Indirect Addressing ............................................................. 18 FSR Register ...................................................... 8, 9, 18 INDF Register ............................................................... 9 Instruction Format ............................................................... 77 Instruction Set ..................................................................... 77 ADDLW ....................................................................... 79 ADDWF ....................................................................... 79 ANDLW ....................................................................... 79 ANDWF ....................................................................... 79 BCF ............................................................................. 79 BSF ............................................................................. 79 BTFSC ........................................................................ 79 BTFSS ........................................................................ 80 CALL ........................................................................... 80 CLRF........................................................................... 80 CLRW ......................................................................... 80 CLRWDT..................................................................... 80 COMF ......................................................................... 80 DECF .......................................................................... 80 DECFSZ...................................................................... 81 GOTO ......................................................................... 81 INCF............................................................................ 81 INCFSZ ....................................................................... 81 IORLW ........................................................................ 81 IORWF ........................................................................ 81 MOVF.......................................................................... 82 MOVLW ...................................................................... 82 MOVWF ...................................................................... 82 NOP ............................................................................ 82 RETFIE ....................................................................... 83 RETLW ....................................................................... 83 RETURN ..................................................................... 83 RLF ............................................................................. 84 RRF............................................................................. 84 SLEEP ........................................................................ 84 SUBLW ....................................................................... 84 SUBWF ....................................................................... 85 SWAPF ....................................................................... 85 XORLW ....................................................................... 85
M
Master Clear (MCLR) MCLR Reset, Normal Operation..................... 64, 69, 70 MCLR Reset, Sleep ........................................ 64, 69, 70 Memory Organization Data Memory ................................................................ 7 Program Memory .......................................................... 7 Microchip Internet Web Site.............................................. 127 Migration from Base-Line to Mid-Range Devices ............. 126 MPLAB ASM30 Assembler, Linker, Librarian ..................... 88 MPLAB ICD 2 In-Circuit Debugger ..................................... 89 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ...................................................... 89 MPLAB Integrated Development Environment Software.... 87 MPLAB PM3 Device Programmer ...................................... 89 MPLAB REAL ICE In-Circuit Emulator System .................. 89 MPLINK Object Linker/MPLIB Object Librarian .................. 88
O
OPCODE Field Descriptions............................................... 77 OPTION Register................................................................ 12 OPTION_REG Register................................................ 10, 12 Oscillator Associated registers ................................................... 33 Oscillator Configuration ................................................ 61, 63 HS......................................................................... 63, 68 LP ......................................................................... 63, 68 RC .................................................................. 63, 64, 68 XT ......................................................................... 63, 68 Oscillator, WDT................................................................... 74
P
Packaging ......................................................................... 121 PDIP Details ............................................................. 122 Paging, Program Memory............................................... 7, 17 PCON Register ............................................................. 16, 68 PICSTART Plus Development Programmer....................... 90 PIE1 Register................................................................ 10, 14 PIR1 Register ................................................................. 9, 15 CCP1IF Bit.................................................................. 15 Pointer, FSR ....................................................................... 18 POR. See Power-on Reset PORTA Associated Registers .................................................. 20
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(c) 2007 Microchip Technology Inc.
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PORTA Register ..................................................... 9, 19 TRISA Register ..................................................... 10, 19 PORTB Associated Registers .................................................. 25 PORTB Register ..................................................... 9, 21 RB Interrupt-on-Change.............................................. 73 RB Interrupt-on-Change Enable (RBIE Bit) ................ 73 RB0/INT Pin, External................................................. 73 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit)........... 73 TRISB Register ..................................................... 10, 21 Power-down Mode. See Sleep Power-on Reset (POR) ..................................... 61, 64, 69, 70 Oscillator Start-up Timer (OST) ............................ 61, 65 Power Control (PCON) Register ................................. 68 Power-down (PD Bit) .................................................. 64 Power-on Reset Circuit, External................................ 64 Power-up Timer (PWRT) ...................................... 61, 65 Time-out (TO Bit) ........................................................ 64 Time-out Sequence..................................................... 68 Time-out Sequence on Power-up ............................... 71 Timing Diagram......................................................... 101 Prescaler Shared WDT/Timer0 ................................................... 28 Switching Prescaler Assignment................................. 28 Program Counter PCL Register........................................................... 9, 17 PCLATH Register ............................................. 9, 17, 73 Reset Conditions......................................................... 69 Program Memory .................................................................. 7 Interrupt Vector ............................................................. 7 Paging..................................................................... 7, 17 Program Memory Map .................................................. 7 Reset Vector ................................................................. 7 Program Verification ........................................................... 76 Programming, Device Instructions ...................................... 77 PWM1CON Register ........................................................... 60 MCLR Reset. See MCLR Power-on Reset (POR). See Power-on Reset (POR) Reset Conditions for PCON Register ......................... 69 Reset Conditions for Program Counter ...................... 69 Reset Conditions for STATUS Register ..................... 69 Timing Diagram ........................................................ 101 WDT Reset. See Watchdog Timer (WDT) Revision History................................................................ 125
S
Shoot-through Current ........................................................ 59 Sleep ...................................................................... 61, 64, 75 Software Simulator (MPLAB SIM) ...................................... 88 Special Event Trigger ......................................................... 40 Special Features of the CPU .............................................. 61 Special Function Registers ................................................... 9 Speed, Operating ................................................................. 1 Stack................................................................................... 17 STATUS Register ............................................................... 11 STATUS Register ........................................................... 9, 73 PD Bit ......................................................................... 64 TO Bit ......................................................................... 64
T
T1CON Register ............................................................. 9, 32 T2CON Register ............................................................. 9, 36 Timer0 ................................................................................ 27 Associated Registers.................................................. 28 External Clock ............................................................ 28 Operation.............................................................. 27, 29 Overflow Flag (T0IF Bit) ............................................. 73 Overflow Interrupt ....................................................... 73 T0CKI ......................................................................... 28 Timing Diagram ........................................................ 102 TMR0 Register ............................................................. 9 Timer1 ................................................................................ 29 Associated registers ................................................... 33 Asynchronous Counter Mode ..................................... 30 Reading and Writing ........................................... 30 Interrupt ...................................................................... 30 Modes of Operation .................................................... 29 Operation During Sleep .............................................. 30 Oscillator..................................................................... 30 Prescaler .................................................................... 30 T1CON Register ........................................................... 9 Timing Diagram ........................................................ 102 TMR1H Register..................................................... 9, 29 TMR1L Register ..................................................... 9, 29 Timer2 Associated registers ................................................... 36 PR2 Register .............................................................. 10 T2CON Register ........................................................... 9 TMR2 Register ............................................................. 9 Timers Timer1 T1CON ............................................................... 32 Timer2 T2CON ............................................................... 36 Timing Diagrams Half-Bridge PWM Output ............................................ 59 PWM Auto-shutdown Auto-restart Enabled........................................... 58 Firmware Restart ................................................ 58 Time-out Sequence on Power-up............................... 71 Timer1 Incrementing Edge ......................................... 31 Wake-up from Sleep via Interrupt............................... 76
R
RA<3 0> ................................................................................ 19 RA4/T0CKI Pin.................................................................... 20 RAM. See Data Memory. RB0 Pin ............................................................................... 21 Reader Response ............................................................. 128 Read-Modify-Write Operations ........................................... 77 Register File .......................................................................... 8 Register File Map .................................................................. 8 Registers ADCON0 (ADC Control 0) .......................................... 41 ADCON1 (ADC Control 1) .......................................... 42 CCP1CON (Enhanced CCP1 Control)........................ 47 CONFIG (Configuration Word).................................... 62 ECCPAS (Enhanced CCP Auto-shutdown Control) ... 57 INTCON (Interrupt Control)......................................... 13 INTCON Register RBIF.................................................................... 21 OPTION_REG (OPTION) ........................................... 12 PCON (Power Control Register) ................................. 16 PIE1 (Peripheral Interrupt Enable 1)........................... 14 PIR1 (Peripheral Interrupt Register 1) ........................ 15 PWM1CON (Enhanced PWM Control) ....................... 60 STATUS...................................................................... 11 T1CON........................................................................ 32 T2CON........................................................................ 36 Reset............................................................................. 61, 64 Brown-out Reset (BOR). See Brown-out Reset (BOR)
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Timing Diagrams and Specifications................................... 98 A/D Conversion ......................................................... 105 Brown-out Reset (BOR) ............................................ 101 Capture/Compare/PWM (CCP)................................. 103 CLKOUT and I/O....................................................... 100 External Clock ............................................................. 98 Oscillator Start-up Timer (OST) ................................ 101 Power-up Timer (PWRT) .......................................... 101 Reset......................................................................... 101 Timer0 and Timer1.................................................... 102 Watchdog Timer (WDT) ............................................ 101
V
VREF. SEE ADC Reference Voltage
W
W Register .......................................................................... 73 Wake-up from Sleep ..................................................... 61, 75 Interrupts ............................................................... 69, 70 MCLR Reset ............................................................... 70 Timing Diagram........................................................... 76 WDT Reset ................................................................. 70 Watchdog Timer (WDT) ................................................ 61, 74 Enable (WDTE Bit)...................................................... 74 Postscaler. See Postscaler, WDT Programming Considerations ..................................... 74 RC Oscillator ............................................................... 74 Time-out Period .......................................................... 74 Timing Diagram......................................................... 101 WDT Reset, Normal Operation ....................... 64, 69, 70 WDT Reset, Sleep .......................................... 64, 69, 70 WWW Address.................................................................. 127 WWW, On-Line Support........................................................ 4
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(c) 2007 Microchip Technology Inc.
PIC16F716
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) PIC16F716 - I/L 301 = Industrial temp., PDIP package, QTP pattern #301. PIC16F716 - E/SO = Extended temp., SOIC package.
Device:
PIC16F716(1), PIC16F716T(2); VDD range 2.0V to 5.5V I E SO P SS = -40C to +85C = -40C to +125C = = = SOIC PDIP SSOP (Industrial) (Extended)
Temperature Range:
Package:
Pattern:
QTP, SQTP, Code or Special Requirements (blank otherwise)
Note 1: 2:
F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel SOIC and SSOP packages only.
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DS41206B-page 133
WORLDWIDE SALES AND SERVICE
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12/08/06
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